Alex Shapiro
July 14, 2016
Abstract
Battery powered devices emphasize energy efficiency in modern sub-22 nm
CMOS microprocessors rendering classic power reduction solutions not
sufficient. Classical solutions that reduce power consumption in high
performance integrated circuits are superseded with novel and enhanced
power reduction techniques to enable the greater energy-efficiency desired
in modern microprocessors and emerging mobile platforms. Dynamic power
consumption is reduced by operating over a wide range of supply voltages.
This region of operation is enabled by a high speed and power efficient
level shifter which translates low voltage digital signals to higher
voltages (and vice versa), a key component that enables communication
among circuits operating at different voltage levels. Additionally,
optimizing the wide supply voltage range of signals propagating across
long interconnect enables greater energy savings. A closed-form delay
model supporting wide voltage range is developed to enable this capability.
The model supports an ultra-wide voltage range from nominal voltages to
subthreshold voltages, and a wide range of repeater sizes. To mitigate
the drawback of lower operating speed at reduced supply voltages, the
high performance exhibited by MOS current mode logic technology is exploited.
High performance and energy efficient circuits are enabled by combining
this logic style with power efficient near threshold circuits. Many-core
systems that operate at high frequencies and process highly parallel
workloads benefit from this combination of MCML with NTC.
Due to aggressive scaling, static power consumption can in some cases
Overshadow dynamic power. Techniques to lower leakage power have therefore
become an important objective in modern microprocessors. To address this
issue, an adaptive power gating technique is proposed. This technique utilizes
high levels of granularity to save additional leakage power when a circuit
is active as opposed to standard power gating that saves static power only
when the entire circuit is powered off. This technique provides significant
savings in static power in addition to standard benefits from classical
power gating.
Improvements in energy efficiency are enabled by reducing both static and
dynamic power consumption utilizing adaptive and near threshold circuit
techniques. These advanced power reduction techniques will enable the greater
energy efficiency required in modern portable systems.