Design and Analysis of On-Chip High Performance Power Distribution Networks

Andrey Mezhiba

March 5, 2004

Abstract

Distributing power in modern high speed, high complexity integrated circuits has become a challenging task. These circuits draw tens of amperes of current from a low voltage power supply, while switching o on-chip loads within tens of picoseconds. Moreover, the on-chip power transients are exacerbated by clock and power gating techniques, which are used to decrease the circuit power consumption. These conditions place strict requirements on the on-chip power distribution networks to ensure the integrity of the on-chip power supply levels and maintain correct circuit operation. The design and analysis of on-chip power distribution networks is the primary subject of this dissertation.

An on-chip power distribution network is a part of a larger power distribution system. This power distribution system, from the voltage regulator through the printed circuit board and pack- age onto the integrated circuit to the power terminals of the on-chip circuitry, spans several tiers of packaging hierarchy. The two primary factors that determine the impedance characteristics of the overall power distribution system are the distribution of decoupling capacitance throughout the system and the inductive characteristics of the comprising interconnect. The impedance characteristics of the on-chip interconnect are particularly crucial to preventing circuit resonances at high frequencies. The impedance characteristics of on-chip multi-layer power distribution grids are analyzed and the effect of these characteristics on the circuit behavior is discussed. The inductance of typical multi-layer grids decreases with frequency while the resistance increases with frequency.

Multi-layer grids are therefore well suited for high speed, low impedance power distribution systems. Inductance/area/resistance tradeoffs in power distribution grids are described in terms of the power supply noise. An efficient method for estimating the impedance characteristics of multi-layer power distribution grid layers is developed. The techniques and methods of analysis developed in this dissertation support the effective design of robust power distribution networks for application in high speed, high complexity integrated circuits.

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