Algorithms, Architectures, and Circuits for VLSI-Based CDMA Communications

Boris D. Andreev

October 18, 2004

Abstract

Spread spectrum CDMA is the core technology for third generation wireless services. The astonishing increase in integrated circuit performance during the past decades has made possible the hardware integration of a growing number of signal processing algorithms. A variety of system and circuit level issues related to CDMA receivers are discussed in this dissertation. Due to the rising complexity of both the VLSI circuits and the related signal processing algorithms, a multilevel design approach has become increasingly complicated.

One of the most unique properties of CDMA technology is that the system capacity is only softly limited by multiuser interference and the characteristics of the receiver. Improvements at any level of the design process can therefore significantly enhance system capacity and efficiency. This characteristic has been demonstrated at the system level by selection of a preferred set of scrambling codes and enhancements in the channel estimation process. At the algorithmic and architectural levels, specific receiver structures are optimized for efficiency and low power consumption. At the circuit level, tapered transmission gate chains and the geometric sizing of CMOS inverters are investigated. The primary goal of this dissertation is to provide specific techniques and strategies for the design of efficient VLSI based CDMA receivers.

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