April 26, 1995
A hybrid radix-4/radix-8 architecture is presented as a compromise between a high speed radix-4 multiplier and a low power radix-8 multiplier. In this hybrid radix-4/radix-8 architecture, the performance bottleneck of radix-8 multiplication, the generation of three times the multiplicand for use in the partial products, is performed in parallel with the radix-4 partial product reduction.
Two specific performance constraining circuit elements are discussed in detail: CMOS tapered buffers and tapered serial MOSFET chains. These circuit elements are common structures in many CMOS-based integrated circuits.
CMOS tapered buffers are used to drive high capacitance nodes within the multiplier. A unified design methodology is developed which simultaneously optimizes speed, power, area, and reliability, the performance criteria of primary importance in the design of tapered buffers. This methodology utilizes new expressions which include the split-capacitor model and the effects of velocity saturation. A refinement of the tapered buffer process is presented which allows the interconnect capacitance between buffer stages to be considered during the design of tapered buffers. It is shown that by considering the local interconnect capacitance during the design phase, the power dissipation, propagation delay, and physical area of the buffer system are each improved.
Finally, transistor channel width tapering of serially connected MOSFETs is presented as a method to decrease the power dissipation and increase the speed of MOSFET chains. Tapering, the process of decreasing the channel width along the serial chain from ground to output, is shown to fall into one of three categories based upon the load capacitance and parasitic capacitances along the serial chain.