Synthesis of Clock Distribution Networks for High Performance VLSI/ULSI-Based Synchronous Digital Systems

Jose Luis Neves

December 8, 1995

Abstract

The automated design of clock distribution networks is a fundamental element in the design and synthesis of VLSI/ULSI-based synchronous digital circuits. Recent approaches have focused on layout-based bottom-up techniques, by routing the clock tree such that the propagation delay from the clock source to any register is minimal. In this dissertation a top-down four phase synthesis methodology for automatically designing high performance, highly reliable clock distribution networks is presented, efficiently optimizing circuit speed with non-zero clock skew while preventing race conditions, reducing sensitivity to process parameter variations, and dissipating less power.

The four phases are: Optimal clock skew scheduling to determine a set of non-zero clock skews and clock path delays that minimize the clock period and prevent race conditions; Topological design to obtain the topology of the clock trees and assign delay to each branch that satisfy the clock skew schedule; Circuit design phase to design the distributed CMOS inverters to emulate each branch delay while reducing the sensitivity to process parameter variations, and decreasing the dynamic and short-circuit power dissipation; and Layout phase to determine constraints on the physical location of the CMOS inverters and the effective impedance of the interconnect lines.

The accuracy and generality of this clock distribution network synthesis methodology has been demonstrated on a suite of ISCAS-89 benchmark circuits. Performance improvements of non-zero clock skew versus zero-clock skew circuit implementations of up to 50% are presented. These clock trees have been validated with SPICE simulations, verifying the accuracy of the implementation of the clock distribution networks. The concept of a permissible range of clock skew is introduced and used to ensure that the worst case values of clock skews due to process parameter variations can be tolerated without creating race conditions. Techniques to reduce the power dissipated within the clock trees are described, and power reductions of up to 25% are presented. Thus an effective design methodology for synthesizing clock distribution networks that exploits non-zero clock skew, reduces power dissipation, and is tolerant to process parameter variations is presented for application to high performance VLSI/ULSI-based synchronous digital systems.

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