Physical Resource Allocation for On-Chip Power Delivery Systems

Renatas Jakushokas

June 27, 2011

Abstract

The technology behind integrated circuits is growing rapidly with billions of devices integrated on the same die. These devices operate at several gigahertz and require tens of watts, with voltage levels below a volt. Highly complicated on-chip networks manage and support the operation of these billions of devices. Resources, such as metal, power, and area, are however limited; these resources must be efficiently utilized. The increase in the number of metal layers within an integrated circuit does not keep up with device scaling, creating challenges in global signaling, synchronization, and power delivery. The objective is to address design, analysis, and optimization challenges for highly complicated structures. Power distribution networks, global signal networks, and monolithic substrate are considered in this dissertation.

An effective impedance model of a monolithic substrate is developed within this dissertation, achieving high accuracy in estimating power/ground noise characteristics. A methodology for simultaneously inserting shields and repeaters is described, optimizing multiple resources for global signal interconnects. A closed-form model of the self- and mutual inductance of an interdigitated power and ground distribution network is described, providing less than 5% error for a typical power distribution network. The optimal width of the metal lines that minimizes the impedance of the power distribution network is determined, significantly enhancing the performance of an integrated circuit. A design methodology is also described for a multi-layer power distribution network, achieving enhanced reliability by equalizing the current density over multiple metal layers. Furthermore, a novel link breaking methodology for a mesh structured power distribution network is introduced, reducing coupling noise while improving the maximum operating frequency, on average, by 12%. Finally, a globally integrated power and clock distribution network is presented which utilizes a single network to distribute both global signals; thereby reducing the metal requirement.

The performance of integrated circuits is highly affected by the power delivery system. The primary focus of this dissertation is the development of design and analysis methodologies for on-chip power delivery systems. Integrated circuits developed with these novel design methodologies will provide higher performance, while simultaneously consuming less power, area, and metal.

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