Repeater Insertion for Driving Resistive Interconnect in CMOS VLSI Circuits

Victor Adler

December 14, 1998

Abstract

The progress of CMOS integrated circuit technology has permitted transistors to operate at extremely high speeds. Simultaneously, improvements in technology have enlarged circuit die sizes and the number of transistors, thus increasing the length (hence the delay) of on-chip interconnections. This decrease in transistor delay and increase in interconnect delay has shifted the performance bottleneck of CMOS integrated circuits from transistors to interconnect. The circuit level design strategy of repeater insertion to reduce the delay of on-chip interconnect and improve the performance of leading edge CMOS technologies is described in this dissertation. An inverter-interconnect model and optimization algorithms are presented to provide a repeater insertion methodology to reduce interconnect delay.

As the length of the interconnections increases, the resistance and capacitance of that interconnect increases linearly with length. Thus the RC delay increases quadratically, severely degrading circuit performance. This RC delay can be reduced through the insertion of repeaters along an interconnect line. A CMOS inverter is used as a repeater to reduce this quadratic increase of RC delay.

A repeater-interconnect model based on the short-channel alpha-power law transistor model is developed to describe repeater insertion in a resistive interconnect line. A closed form expression describing the number and size of repeaters to insert along an interconnect line is presented. The analytical expression is generally within 10% of SPICE.

The repeater insertion model for RC lines is expanded for the more general purpose of repeater insertion in RC tree structures. Local and global optimization algorithms are presented to insert repeaters into RC trees. Applications of the repeater insertion methodologies can be used to either minimize average delay or achieve a target delay. Repeater insertion methods reduce delay over typical cascaded buffers by 25% to 60% and are accurate to within 10% of SPICE. Expressions to analytically determine dynamic and short-circuit power dissipation of repeaters in RC trees are also presented. Thus, an integrated methodology for repeater insertion composed of circuit models, insertion algorithms, and demonstration examples is presented for application to high performance VLSI circuits.

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