National Science Foundation

  • RIA: Clock Distribution Design and Register Allocation in Pipelined Systems with Application to Behavioral Synthesis

  • Automated Synthesis of High Performance Clock Distribution Networks

  • Synchronous VLSI Circuit Optimization via Integrated Retiming and Clock Scheduling

  • NIRT:Optical Interconnects for High Performance Processors: Architectures, Circuits, and Devices

  • Design Methodologies and Algorithms for Three-Dimensional Integrated Systems

  • CPA-DA: Integrated Methodology for Managing Noise in Next Generation Multi-Core SoCs

  • 3D-Integrated Intra-Chip Free-Space Optical Interconnect for Future Multi-Core SoCs

    • For further information regarding the NSF, visit http://www.nsf.gov