Semiconductor Research Corporation

  • On-Chip Interconnect Noise in Global Distribution Networks

  • Noise-Aware Design Methodologies for High Performance Clock and Power Distribution Networks

  • Placement of On-Chip Decoupling Capacitors

  • NSF-SRC Initiative for Nanotechnology: Design Methodologies and Algorithms for Three-Dimensional Integrated Systems

  • NSF-SRC Initiative for Nanotechnology: CPA-DA: Integrated Methodology for Managing Noise in Next Generation Multi-Core SoCs

    Software program for inserting repeaters for driving RLC global interconnect networks.

    • For further information regarding the SRC, visit http://www.src.org