Publications - Michael Huang

HyperTEE: A Decoupled TEE Architecture with Secure Enclave Management, Y. Bai, P. Li, Y. Huang, M. Huang, S. zhao, L. Zhao, F. Zhang, D. Meng, R. Hou, Proc. of the 57^thInternational Symposium on Microarchitecture, (MICRO’24) Nov. 2024
DS-GL: Advancing Graph Learning via Harnessing Nature’s Power within Scalable Dynamical Systems, R. Song, C. Wu, C. Liu, A. Li, M. Huang, T. Geng, Proc. of the 51^stInternational Symposium on Computer Architecture (ISCA’24) June 2024
Extending Power of Nature from Binary to Real-Valued Graph Learning in Real World, C. Wu, R. Song, C. Liu, Y. Yang, A. Li, M. Huang, T. Geng, Proc. of the 12^th International Conference on Learning Representations, May 2024
Augmenting an electronic Ising machine to effectively solve boolean satisfiability, A Sharma, M. Burns, A. Hahn & M. Huang, Scientific Reports 13, 22858 (2023), Dec. 2023
Supporting Energy-Based Learning with an Ising Machine Substrate: A Case Study on RBM, U. Vengalam, Y. Liu, T. Geng, H. Wu, M. Huang, in Proc. 56^th International Symposium on Microarchitecture (MICRO’23), Oct. 2023
Combining Cubic Dynamical Solvers with Make/Break Heuristics to Solve SAT, A. Sharma, M. Burns, and M. Huang, in Proc. of 26^th International Conference on Theory and Applications of Satisfiability Testing (SAT) 2023
Ising-CF: A Pathbreaking Collaborative Filtering Method Through Efficient Ising Machine Learning, Z. Liu, Y. Yang, Z. Pan, A. Sharma, A. Hasan, C. Ding, A. Li, M. Huang, T. Geng, Proceedings of the 59^thACM/IEEE Design Automation Conference, Jul. 2023
Ising-Traffic: An Ising-based Framework for Traffic Congestion Prediction with Uncertainty, Z. Pan, A. Sharma, J. Hu, Z. Liu, A. Li, H. Liu, M. Huang, T. Geng, Proceedings of the 37^thAAAI Conference on Artificial Intelligence, Feb. 2023
Increasing Ising Machine Capacity with Multi-Chip Architectures, Anshujit Sharma, Richard Afoakwa, Zeljko Ignjatovic, and Michael Huang, Proceedings of the 49^th International Symposium on Computer Architecture, Jun. 2022 (ISCA’22)
HyBP: Hybrid Isolation-Randomization Secure Branch Predictor, Lutan Zhao, Peinan Li, Rui Hou, Michael Huang, Xuehai Qian, Lixin Zhang, and Dan Meng, Proceedings of the 28^th International Symposium on High-Performance Computer Architecture, Feb. 2022 (HPCA’22)
A Lightweight Isolation Mechanism for Secure Branch Predictors, Lutan Zhao, Peinan Li, Rui Hou, Michael Huang, Jiazhen Li, Lixin Zhang, Xuehai Qian, and Dan Meng; ACM/IEEE Design Automation Conference Dec, 2021 (DAC’21)
Exploiting Security Dependence for Conditional Speculation Against Spectre Attacks, Lutan Zhao, Peinan Li, Rui Hou, Michael Huang, Peng Liu, Lixin Zhang, and Dan Meng; IEEE Transactions on Computers 70(7):963-978, July, 2021 (TC’21)
BRIM: Bistable Resistively-Coupled Ising Machine, Richard Afoakwa, Yiqiao Zhang, Uday Kumar Reddy Vengalam, Zeljko Ignjatovic, and Michael Huang, Proceedings of the 27^thInternational Symposium on High-Performance Computer Architecture, Feb./Mar. 2021 (HPCA’21)
To Stack or Not to Stack, Richard Afoakwa, Lejie Lu, Hui Wu, and Michael Huang,Proceedings of the 28^th International Conference on Parallel Architecture and Compilation Techniques, Sep. 2019
Concurrent Multipoint-to-Multipoint Communication on Interposer Channels, Lejie Lu, Richard Afoakwa, Michael Huang, and Hui Wu, Proceedings of the 2019 International Symposium on Low Power Electronics and Design, July 2019
Bootstrapping: Using SMT Hardware to Improve Single-Thread Performance, Sushant Kondguli and Michael Huang, Proceedings of the 24^th International Conference on Architectural Support for Programming Languages and Operating Systems, Apr. 2019 (ASPLOS’19)
R3-DLA (Reduce, Reuse, Recycle): A More Efficient Approach to Decoupled Look-Ahead Architectures, Sushant Kondguli and Michael Huang, Proceedings of the 25^thInternational Symposium on High-Performance Computer Architecture, Feb. 2019 (HPCA’19)
Division of Labor: A More Effective Approach to Prefetching, Sushant Kondguli and Michael Huang, Proceedings of the 45^th International Symposium on Computer Architecture, June 2018 (ISCA’18)
A Case for a More Effective, Power-Efficient Turbo Boosting, Sushant Kondguli and Michael Huang, ACM Transactions on Architecture and Code Optimization, 15(1):5:1-5:22, Mar 2018
T2: A Highly Accurate and Energy Efficient Stride Prefetcher, Sushant Kondguli and Michael Huang, Proceedings of the International Conference on Computer Design, Nov 2017
Redundant Memory Array Architecture for Efficient Selective Protection, Ruohuang Zheng and Michael Huang, Proceedings of the 44^th International Symposium on Computer Architecture, June 2017 (ISCA’17)
Venice: Exploring Server Architectures for Effective Resource Sharing, Jianbo Dong, Rui Hou, Michael Huang, Tao Jiang, Boyan Zhao, Sally A. McKee, Haibin Wang, Xiaosong Cui, and Lixin Zhang, Proceedings of the 22^nd International Symposium on High-Performance Computer Architecture, Mar. 2016 (HPCA’16)
Building Expressive and Area-Efficient Directories with Hybrid Representation and Adaptive Multi-granular Tracking, Peng Liu, Lei Fang, Michael Huang, and Qi Hu,IEEE Transactions on Computers 2015
Accelerating Decoupled Look-ahead via Weak Dependence Removal: A Metaheuristic Approach, Raj Parihar and Michael Huang, Proceedings of the 20^th International Symposium on High-Performance Computer Architecture, Feb. 2014 (HPCA’14)
Building Expressive, Space-Efficient Coherence Directories, Lei Fang, Peng Liu, Qi Hu, Michael Huang, and Guofan Jiang, Proceedings of International Conference on Parallel Architectures and Compilation Techniques, Sep. 2013
Enhancing Effective Throughput for Transmission Line-Based Bus, Aaron Carpenter, Jianyun Hu, Ovunc Kocabas, Michael Huang, and Hui Wu, Proceedings of the 39^thInternational Symposium on Computer Architecture, Jun. 2012 (ISCA’12)
Using Transmission Lines for Global On-Chip Communication, Aaron Carpenter, Jianyun Hu, Jie Xu, Michael Huang, Hui Wu, and Peng Liu, Journal for Emerging and Selected Topics in Circuits and Systems 2(2):183-193, Jun. 2012.
3-D Integrated Heterogeneous Intra-Chip Free-Space Optical Interconnect, Berkehan Ciftcioglu, Rebecca Berman, Shang Wang, Jianyun Hu, Ioannis Savidis, Manish Jain, Duncan Moore, Michael Huang, Eby G. Friedman, Gary Wicks, and Hui Wu , Optical Express, 20(4):4331-4345, Feb. 2012
Nanospintronics Based on Magnetologic Gates, Hanan Dery, Hui Wu, Berkehan Ciftcioglu, Michael Huang, Yang Song, Roland Kawakami, Jing Shi, Ilya Krivorotov, Igor Zutic, and Lu J. Sham, IEEE Transactions on Electron Devices, 59(1):259-262, Jan. 2012
Speculative Parallelization in Decoupled Look-ahead, Alok Garg, Raj Parihar, and Michael Huang, Proceedings of Int’l Conference on Parallel Architectures and Compilation Techniques, Oct. 2011
POPS: Coherence Protocol Optimization for both Private and Shared Data, Hemayet Hossain, Sandhya Dwarkadas, and Michael Huang, Proceedings of Int’l Conference on Parallel Architectures and Compilation Techniques, Oct. 2011
A Design Space Exploration for of Transmission-Line Links for On-Chip Interconnect, Aaron Carpenter, Jianyun Hu, Michael Huang, Hui Wu, and Peng Liu, Proceedings of the International Symposium on Low Power Electronics and Design, Aug. 2011
A Case for Globally-Shared-Medium On-Chip Interconnect, Aaron Carpenter, Jianyun Hu, Jie Xu, Michael Huang, and Hui Wu, Proceedings of the 38^th International Symposium on Computer Architecture, Jun. 2011 (ISCA’11)
A 3-D Integrated Intrachip Free-Space Optical Interconnect for Many-Core Chips, Berkehan Ciftcioglu, Rebecca Berman, Jian Zhang, Zach Darling, Shang Wang, Jianyu Hu, Jing Xue, Alok Garg, Manish Jain, Ioannis Savidis, Duncan Moore, Michael Huang, Eby Friedman, Gary Wicks, and Hui Wu, IEEE Photonics Technology Letters, 23(3):164-166, Feb. 2011
Efficient Data Streaming with On-chip Accelerators: Opportunities and Challenges, Rui Hou, Lixin Zhang, Michael C. Huang, Kun Wang, Hubertus Franke, Yi Ge, and Xiaotao Chang, Proceedings of the 17^th International Symposium on High-Performance Computer Architecture, Feb. 2011 (HPCA’11)
Particle-in-cell simulations with charge-conserving current deposition on graphic processing units, Xianglong Kong, Michael Huang, Chuang Ren and Viktor Decyk, Journal of Computational Physics, 230(4):1676-1685, Feb. 2011
A Realistic Evaluation of Memory Hardware Errors and Software System Susceptibility, Xin Li, Michael Huang, Kai Shen, and Lingkun Chu, Proceedings of the 2010 USENIX Annual Technical Conference, Jun. 2010
An Intra-Chip Free-Space Optical Interconnect, Jing Xue, Alok Garg, Berkehan Ciftcioglu, Shang Wang, Jianyun Hu, Ioannis Savidis, Manish Jain, Peng Liu, Michael Huang, Hui Wu, Eby G. Friedman, Gary Wicks, Duncan Moore, Proceedings of the 37^thInternational Symposium on Computer Architectures, Jun. 2010 (ISCA’10) Extended technical report
DDCache: Decoupled and Delegable Cache Data and Metadata, Hemayet Hossain, Sandhya Dwarkadas, and Michael Huang, Proceedings of the 18^th International Conference on Parallel Architectures and Compilation Techniques, Sep. 2009
Replacing Associative Load Queues: A Timing-Centric Approach, Fernando Castro, Regana Noor, Alok Garg, Dani Chaver, Michael Huang, Luis Pinuel, Manuel Prieto, and Franciso Tirado, IEEE Transactions on Computers, 58(4):496-511, Apr. 2009
Variation-Tolerant Hierarchical Voltage Monitoring Circuit for Soft Error Detection, Ashay Narsale and Michael Huang, Proceedings of the 10^th International Symposium on Quality Electronic Design, Mar. 2009
A Performance-Correctness Explicitly-Decoupled Architecture, Alok Garg and Michael Huang, Proceedings of the 41^st International Symposium on Microarchitecture, pp. 306-317, Nov. 2008 (MICRO’08) Extended technical report
Improving Support for Locality and Fine-Grain Sharing in Chip Multiprocessors, Hemayet Hossain, Sandhya Dwarkadas, and Michael Huang, Proceedings of the 17^thInternational Conference on Parallel Architectures and Compilation Techniques, Oct. 2008
Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-Performance Microprocessors, Lin Zhang, Aaron Carpenter, Berkehan Ciftcioglu, Alok Garg, Michael Huang, and Hui Wu, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 16(9):1251-1256, Sep. 2008 Extended technical report
Supporting Highly-Decoupled Thread-Level Redundancy for Parallel Programs, M. Wasiur Rashid and Michael Huang, Proceedings of the International Symposium on High-Performance Computer Architecture, Feb. 2008, pp. 393-404 (HPCA’08)
An Empirical Study of Memory Hardware Errors in a Server Farm, Xin Li, Michael Huang, Kai Shen, and Lingkun Chu, Proceedings of the 3^rd Workshop on Hot Topics in System Dependability, June 2007
A Memory Soft Error Measurement on Production Systems, Xin Li, Kai Shen, Michael Huang, and Lingkun Chu, Proceedings of the 2007 USENIX Annual Technical Conference, June. 2007
DMDC: Delayed Memory Dependence Checking through Age-Based Filtering, Fernando Castro, Luis Pinuel, Dani Chaver, Manuel Prieto, Michael Huang, and Francisco Tirado, Proceedings of the 38^th International Symposium on Microarchitecture, Dec. 2006, pp. 297-306 (MICRO’06)
Substituting Associative Load Queue with Simple Hash Table in Out-of-Order Microprocessors, Alok Garg, Fernando Castro, Michael Huang, Luis Pinuel, Dani Chaver, and Manuel Prieto, Proceedings of the International Symposium on Low-Power Electronics and Design, Oct. 2006, pp. 268-273
Injection-Locked Clocking: A New GHz Clock Distribution Scheme, Lin Zhang, Berkehan Ciftcioglu, Michael Huang, Hui Wu, Proceedings of the IEEE Custom Integrated Circuits Conference, Sep. 2006
SEED: Scalable, Efficient Enforcement of Dependences, Francisco J. Mesa-Martinez, Michael Huang, and Jose Renau, Proceedings of the 15^th International Conference on Parallel Architectures and Compilation Techniques, Sep. 2006, pp. 254–264
Slackened Memory Dependence Enforcement: Combining Opportunistic Forwarding with Decoupled Verification, Alok Garg, M. Wasiur Rashid, and Michael Huang,Proceedings of the International Symposium on Computer Architecture, Jun. 2006, pp. 142-153 (ISCA’06) Extended technical report
A Load-Store Queue Design based on Predictive State Filtering, Fernando Castro, Daniel Chaver, Luis Pinuel, Manuel Prieto, Michael Huang, and Francisco Tirado, Journal of Low Power Electronics 2(1):27-36, Apr. 2006
Software-Hardware Cooperative Memory Disambiguation, Ruke Huang, Alok Garg, and Michael Huang, Proceedings of the International Symposium on High-Performance Computer Architecture, Feb. 2006, pp. 248-257 (HPCA’06) Extended technical report
Power Efficient Error Tolerance in Chip Multi-Processors, M. Wasiur Rashid, Ed Tan, Michael Huang, and David Albonesi, IEEE Micro 25(6):60-70, Nov./Dec. 2005 Special Issue on Reliability-Aware Design
Load-Store Queue Management: an Energy Efficient Design based on a State Filtering Mechanism, Fernando Castro, Daniel Chaver, Luis Piñuel, Manuel Prieto, Michael Huang, and Francisco Tirado, Proceedings of the 2005 IEEE International Conference on Computer Design, Oct. 2005, pp. 617-624
A Power-Efficient and Scalable Load-Store Queue Design, Fernando Castro, Daniel Chaver, Luis Piñuel, Manuel Prieto, Michael Huang, and Francisco Tirado, Proceedings of the International Workshop on Power And Timing Modeling, Optimization and Simulation , Sep. 2005, appears in Lecture Notes in Computer Science (LNCS) Vol. 2236(8):1-9, 2005 by Springer Verlag
Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault Tolerance, M. Wasiur Rashid, Ed Tan, Michael Huang, and David Albonesi, Proceedings of the 14^thInternational Conference on Parallel Architectures and Compilation Techniques, Sep. 2005, pp. 315-325
Energy-Aware Fetch Mechanism: Trace Cache and BTB Customization, Daniel Chaver, Miguel Rojas, Luis Piñuel, Manuel Prieto, Francisco Tirado, and Michael Huang, Proceedings of the International Symposium on Low-Power Electronics and Design, Aug. 2005, pp. 42-47
EXPERT: Expedited Simulation Exploiting Program Behavior Repetition, Wei Liu and Michael Huang Proceedings of the International Conference on Supercomputing, Jun. 2004, pp. 126-135
Dynamically Reducing Pressure on the Physical Register File through Simple Register Sharing (Winner of Best Paper Award), Liem Tran, Nick Nelson, Fung Ngai, Steve Dropsho, and Michael Huang Proceedings of the International Symposium on Performance Analysis of Systems and Software, Mar. 2004, pp. 78-87
The Thrifty Barrier: Energy-Efficient Synchronization in Shared-Memory Multiprocessors, Jian Li, José Martínez, and Michael Huang, Proceedings of the International Symposium on High-Performance Computer Architecture, Feb. 2004, pp. 14-23 (HPCA’04)
Dynamically Tuning Processor Resources with Adaptive Processing, David Albonesi, Rajeev Balasubramonian, Steven Dropsho, Sandhya Dwarkadas, Eby Friedman, Michael Huang, Volkan Kursun, Grigorios Magklis, Michael Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter Cook, and Stanley Schuster, IEEE Computer 36(12):49-58, Dec. 2003 Special issue on Power-Aware and Temperature-Aware Computing
Customizing the Branch Predictor to Reduce Complexity and Energy Consumption, Michael Huang, Daniel Chaver, Luis Piñuel, Manuel Prieto, and Francisco Tirado, IEEE Micro 23(5):12-25, Sep./Oct. 2003 Special issue on Power and Complexity Aware Design
Branch Prediction On Demand: an Energy-Efficient Solution, Daniel Chaver, Luis Piñuel, Manuel Prieto, Francisco Tirado, and Michael Huang, Proceedings of the International Symposium on Low-Power Electronics and Design, Aug. 2003, pp. 390 – 395
Positional Processor Adaptation: Application to Energy Reduction, Michael Huang, Jose Renau, and Josep Torrellas, Proceedings of the 30^th International Symposium on Computer Architecture, Jun. 2003, pp. 157-168
Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors, José Martínez, Jose Renau, Michael Huang, Milos Prvulovic, and Josep Torrellas, Proceedings of the 35^th International Symposium on Microarchitecture, Nov. 2002, pp. 3-14 (MICRO’02)
Energy-Efficient Hybrid Wakeup Logic, Michael Huang, Jose Renau, and Josep Torrellas, Proceedings of the International Symposium on Low-Power Electronics and Design, Aug. 2002, pp. 196-201
The Design of DEETM: a Framework for Dynamic Energy Efficiency and Temperature Management, Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas, Journal of Instruction-Level Parallelism, Vol. 3, 2002
Profile-Based Energy Reduction in High-Performance Processors, Michael Huang, Jose Renau, Josep Torrellas, Proceedings of the 4^th ACM Workshop on Feedback-Directed and Dynamic Optimization, Dec. 2001
L1 Data Cache Decomposition for Energy Efficiency, Michael Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas, Proceedings of the International Symposium on Low-Power Electronics and Design, Aug. 2001, pp. 10-15
A Framework for Dynamic Energy Efficiency and Temperature Management, Michael Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas, Proceedings of the 33^rd International Symposium on Microarchitecture, Dec. 2000, pp. 202-213 (MICRO’00)
Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips, Michael Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas, Proceedings of the 2^ndWorkshop on Intelligent Memory Systems, Nov. 2000. Also appears in Lecture Notes in Computer Science (LNCS) Vol. 2107(VIII):152-159 by Springer Verlag
FlexRAM: Toward an Advanced Intelligent Memory System, (Winner of High-Impact Paper Award) Yi Kang, Michael Huang, Seung-Moon Yoo, Diana Keen, Zhenzhou Ge, Vinh Lam, Pratap Pattnaik and Josep Torrellas, Proceedings of the 1999 IEEE International Conference on Computer Design, Oct. 1999, pp. 192-201