August 8, 2007
The higher switching speed of a greater number of smaller transistors produces faster and larger current transients in the power distribution network. These conditions place strict requirements on the on-chip power distribution network to ensure the integrity of the on-chip power supply.
To manage the problem of high power dissipation, multiple on-chip power supply voltages have become commonplace in nanoscale integrated circuits. On-chip power distribution grids with multiple power supply voltages and multiple grounds are presented in this dissertation. The impedance characteristics of the power distribution grids with multiple power supply voltages and multiple grounds are described. The proposed power distribution grid structures are shown to outperform traditional power distribution grids with multiple power supply voltages and a single ground.
Decoupling capacitors are widely used to manage power supply noise. Conventional approaches for placing on-chip decoupling capacitors is shown to be ineffective in nanoscale integrated circuits. A design methodology for placing on-chip decoupling capacitors based on the maximum effective radii is described in this dissertation. Techniques to estimate the minimum required on-chip decoupling capacitance are presented.
A methodology for designing decoupling capacitors for power distribution systems with multiple power supply voltages is also described.
As the minimum feature size continues to scale, additional on-chip decoupling capacitance will be required to support increasing current demands. A larger on-chip decoupling capacitance requires a greater area which cannot conveniently be placed in proximity of the switching circuits. A system of distributed on-chip decoupling capacitors is shown to be a good compromise, providing the required charge drawn by the load while satisfying existing technology constraints. The research presented in this dissertation provides specific methodologies, techniques, and strategies for designing robust on-chip power distribution networks with on-chip decoupling capacitors for application to high performance nanoscale integrated circuits.