On-Chip Interconnect Noise in High Performance CMOS Integrated Circuits

Tianwen (Kevin) Tang

July 20, 2000

Abstract

As the feature size of on-chip devices and interconnections scales down to very deep submicrometer (VDSM) dimensions, the chip size has also increased, while the operating frequencies have begun to exceed a gigahertz. Serious on-chip electrical problems are being encountered in these high speed, VDSM high complexity circuits. These problems include the degradation of signal quality due to parasitic interconnect impedances, signal distortion along coupled interconnect lines, voltage fluctuations in the power distribution network, and substrate coupling, each of which are major sources of on-chip noise in high speed CMOS integrated circuits.

A physically oriented approach is presented to integrate noise information into the process of designing CMOS integrated circuits -- Design for Noise (DFN). A bottom-up methodology, based on a nonlinear device model and on-chip interconnect impedances, is applied in the development of analytic models that characterize the timing and power properties of a CMOS logic gate driving an interconnect line. Signal waveform and coupling noise are also characterized based on a capacitively and inductively coupled interconnect model. The power distribution network is investigated in terms of simultaneous switching, transient current rate, signal activity, and related circuit design constraints.

Circuit design strategies that satisfy delay, power, and signal integrity constraints have been developed. Methodologies for designing the power distribution networks with appropriate width and spacing are presented that account for the effects of on-chip inductance, transient IR voltage drops, and simultaneous switching noise with an overall goal of minimizing logic delay uncertainty.

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