November 16, 2004
An analysis of clock feedthrough in CMOS analog transmission gate switches is presented in this dissertation. A clock feedthrough mechanism and a related model of a transmission gate switch are established in the current-voltage domain. Region and zone maps of the transmission gate during switch off are developed and used to efficiently estimate clock feedthrough noise.
The charge-sharing effect (CSE) in switched-capacitor CMOS circuits is studied and evaluated. A technique using Miller capacitance in a sample-and-hold circuit is introduced to reduce the charge sharing effect caused by the parasitic capacitance and clock feedthrough from a sampling switch. A ten times reduction in CSE and clock feedthrough is achieved.
An on-chip circuit has also been developed to directly measure substrate and line-to-line coupling noise voltages and waveforms. This test circuit has been manufactured in a 0.35 µm CMOS process and consists of noise generators and switched-capacitor signal processing circuitry. The experimental data show that on-chip generators ranging in area from 1 µm2 to 6 µm2 produce noise at the receiver, decreasing from 3.14 mV/µm to 0.73 mV/µm. The efficiency in reducing substrate noise by including substrate guard rings has also been studied and evaluated in this research effort. Supported by experiment measurement, open loop and closed guard rings reduce the noise by 20% and 85%, respectively. The difference between experimental and an analytic model of the line-to-line coupling capacitance ranges from 8.5% to 17.7% for different metal layers.