In this research, we are exploiting on-chip voltage regulators as a countermeasure against side-channel attacks with circuit and architectural level techniques. We currently focus on switching voltage converters (switched capacitor and buck) and exploit the non-injective relationship between the input and output power profiles of these voltage converters. We recently proposed converter-gating (CoGa) and converter-reshuffling (CoRe) techniques to break the one-to-one relationship of the input and output power profiles of a SC voltage converter.
On-chip voltage regulation
On-chip voltage regulation has recently drawn a lot of attention in both mobile and server processors. In this research, an ultra-low area, current efficient voltage regulator appropriate for distributed point-of-load voltage regulation in high performance integrated circuits (ICs) is proposed. The proposed voltage regulator is a hybrid combination of a switching voltage regulator and a linear voltage regulator. The regulator occupies ~0.015 mm² on-chip are while proving up to 80 mA output current. The proposed circuit therefore provides a means for distributing multiple local power supplies across an integrated circuit, maintaining high current efficiency and small area.
3-D integration is an important enabling technology for the continued growth of advanced computing systems. By vertically stacking two-dimensional (2-D) planes, 3-D integration allows for a drastic reduction in interconnect length, resulting in reduced delay and power. Since in 3-D integration multiple planes are stacked, this technology facilitates heterogeneous systems where different planes are dedicated to a specific function, such as digital signal processing, communications, and imaging. Power network design is however significantly more complicated in heterogeneous 3-D circuits. Algorithms and design methodologies are required to determine the optimum location of not only the on-chip power supplies and decoupling capacitors, but also the vertical through silicon vias (TSVs) which provide connections between the vertically stacked planes. We designed and tested a 3-D test circuit, composed of three vertically bonded wafers with TSVs, to evaluate the effect of different power delivery topologies, TSV densities, and decoupling capacitors on P/G noise.
Power grid analysis
The analysis of power grids in high performance integrated circuits has become a significant challenge in circuit verification due to the high complexity of the power grids. Fast algorithms are required to efficiently analyze large power grids within reasonable time. Closed-form expressions and related algorithms for fast power grid analysis are proposed in this research. An effective resistance model is proposed for semi-uniform power grids. The principle of spatial locality is exploited to accelerate the proposed power grid analysis process. Since no iterations are required for the proposed IR drop analysis, the proposed algorithms are significantly faster as compared to the existing power grid analysis techniques. This method exhibits less than 0.3% error.
Distributed power delivery
With each technology generation, the power delivery network becomes larger and more complicated, makingthe system analysis process computationally complex. The rising number of on-chip power supplies and intentional decoupling capacitors inserted throughout an integrated circuit further complicates the analysis of the power distribution network. Interactions among the on-chip power supplies, decoupling capacitors, and load circuitry are investigated in this research. The on-chip power supplies and decoupling capacitors within the power network are simultaneously co-designed and placed. The effect of physical distance on the power supply noise is investigated. This methodology changes conventional practices where the power distribution network is designed first, followed by the placement of the decoupling capacitors.
Noise aware interconnect design
P/G networks are routed as shield lines in passive shielding to mitigate coupling noise. These P/G shield lines themselves can, however, be noisy. This noise, typically neglected in existing shielding methodologies, is due to inductive noise and resistive voltage drops. Design guidelines for shielding in the presence of power/ground (P/G) noise are presented in this research. The effect of P/G noise on crosstalk is analyzed for different line lengths, line widths, and interconnect driver resistances. Considering the P/G noise, a shield line can degrade rather than enhance signal integrity due to increased P/G noise coupling on the victim line. Physical spacing and shield insertion are compared in terms of the coupling noise on the victim line for several technology nodes. Boundary conditions are also provided to determine the effective range of spacing and shield insertion in the presence of P/G noise. Additionally, the effects of technology scaling on P/G noise and shielding efficiency are discussed, and related design tradeoffs are addressed.