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Low Power, Gigahertz Clock Generation and Distribution using Injection-Locked Oscillators

Lin Zhang

Prof. Hui Wu

CSB 523

Abstract

The generation and distribution of high speed and high quality clock signals have become increasingly important in high performance microprocessors, wireline communications and wireless communications. In multi-gigahertz frequency range, conventional clocking techniques have encountered several design challenges in terms of power consumption, skew and jitter. Injection-locking is a promising technique to address these design challenges for gigahertz clocking. This dissertation presents our studies of gigahertz, high performance, low power clock generation and distribution using injection-locked frequency dividers (ILFDs), injection-locked frequency multipliers (ILFMs) and injection-locked clock distribution networks (ILCs). Chip prototypes in 0.18um standard digital CMOS technologies are demonstrated for the following gigahertz clocking circuits. For gigahertz clock generation, we introduced a phase tuning scheme for injection-locked frequency divider based dual-phase signal generators. The phase tuning capability in this scheme comes from the tunable phase transfer characteristics of injection-locked frequency dividers. Implemented with a frequency-tunable double-balanced divide-by-two injection-locked frequency divider, the dual-phase signal generator prototype achieves 100° differential phase tuning range around quadrature with generated signal frequency of 5 GHz. For gigahertz frequency division, we introduced a divide-by-odd-number injection-locked frequency divider to address the division ratio limitation of conventional injection-locked frequency dividers. With differential injection and harmonic filtering, this new ILFD topology maintains the fully differential nature of the output signal, while at the same time achieves effective mixing between the injected odd harmonics and output oscillation. 5% locking range without frequency tuning is achieved for the circuit prototype of this topology working at input frequency of 16-18 GHz. For gigahertz frequency multiplication, we introduced an injection-locked oscillator to work as a high gain, high Q harmonic filter for conventional harmonic-generation and-filtering frequency multipliers. This new approach achieves significant better undesired harmonic suppression for frequency multipliers built with lossy digital CMOS processes. Frequency tunability of injection-locked oscillators also enables multi-mode operations for such injection-locked frequency multipliers. The circuit prototype of such a frequency multiplier achieves multiply by 2 and 3 dual-mode operation with undesired harmonic suppressions better than 30 dB achieved for both modes. For gigahertz clock distribution, we proposed injection-locked clocking using injection-locked oscillators as the local clock regenerators. Because of ILO's capability to be locked by a small input signal, this new approach reduced a large amount of clock buffers in global clock distribution. This not only reduces the power consumption, but also reduces the skew and jitter which come from these clock buffers. The phase tenability of ILOs can also be utilized to achieve the deskew function between different clock domains. Three ILC circuit prototypes working at several gigahertz demonstrated the better power and jitter performance and the built-in deskew capability of ILC.