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Power Delivery in High Current 3-D Systems

Kan Xu

Supervised by Professor Eby Friedman

Join Zoom Meeting https://rochester.zoom.us/j/95804101704

Although CMOS scaling has slowed, the demand for greater performance and heterogeneous integration has yet to end. Greater performance generally leads to higher current demand in high performance computing (HPC) systems. Three-dimensional (3-D) integrated circuits are a natural platform for heterogeneous integration. A 3- D HPC system however suffers from challenging design issues in the power delivery systems due to high current demand and vertical integration.

The dissertation starts by addressing two primary challenges, power noise and electromigration, within high current on-chip power systems. An exploratory model of an on-chip power grid and several on-chip metalization schemes are proposed to mitigate power noise. It is observed that the effectiveness of different metalization schemes on suppressing power noise varies significantly among different advanced technology nodes. To further address the issue of electromigration, voltage stacking is exploited. Parasitic impedance-aware load balancing circuits are proposed to manage load variations across different layers.

Moreover, two critical parameters at the package and board levels, electromagnetic interference (EMI) and “last inch power loss,” in 2.5-D power systems are discussed. A novel resonant converter with a distributed topology is proposed to mitigate EMI. Two VR-on-package topologies, VR-top and -bottom, are described. The impedance characteristics, EMI, power noise, and power loss of these two VR-on-package topologies are compared.

To fully exploit the potential of 3-D HPC systems, current paths within 3-D integrated power systems are explored. A 3-D redistribution layer (RDL), affecting both the vertical and 2-D current paths, is introduced. The effects of through silicon via (TSV) manufacturing processes and stacking topologies on RDLs are presented. A novel grid-based RDL topology is also proposed to support high current 3-D power systems while exhibiting low power noise. The advantages of a grid-based RDL for a nonuniform TSV distribution are also discussed. 3-D HPC systems are an excellent candidate to achieve high performance as well as heterogeneity. Vertical current path-aware design methodologies are critical to support reliable, power efficient, and high current 3-D power systems. This dissertation provides insight and solutions regarding the challenges of high current 3-D power systems.