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Assistant Professors Hanan Dery, Michael Huang, and Hui Wu (left to right, below) recently won NSF awards to pursue their research over the next few years. Dr. Dery's NSF award supports his spintronics work. Dr. Huang's NSF CAREER award supports his research into a computer architecture design that improves computer speed by decoupling performance from correct instruction execution. Dr. Wu's NSF award supports his project, 3D-Integrated Intra-Chip Free-Space Optical Interconnect for Future Multi-Core SoCs.

Dr. Dery's NSF award is for almost half a million dollars and supports his spintronics work between now and mid-2011. Joining Dr. Dery on the project, Semiconductor Spintronics Devicees and Circuits, are co-principal investigators Professor Roman Sobolewski and Assistant Professor Huang.

The spintronics project will explore the intrinsic differences between spin-based electronics and conventional electronics in terms of their benefit to information processing. The research has a two-prong strategy.

First, it will extend Dr. Dery's previous research and involve the design and characterization of hybrid lateral semiconductor/ferromagnet devices that are based on spin-accumulation. The external control of these devices is achieved using both electrical and magnetic signals. The group will use advanced magneto-optical techniques to probe the physics of the devices.

Second, the team will study new methods of interconnecting spin-based logic gates to enable large-scale spintronics circuits. This work may include the creation of new integrated CMOS architecture and possible spintronics devices.

Dr. Huang's NSF CAREER award is for $350,000 and supports his research into a computer architecture design that improves computer speed by decoupling performance from correct instruction execution. The CAREER award is one of the most prized honors that a young faculty member can receive and recognizes a strong commitment to both innovative research and teaching.

The goal of Huang's five-year CAREER project is to separate circuitry that will make a computer chip operate quickly from circuitry that will guarantee that the execution of an instruction is correct. Huang calls his solution, explicitly-decoupled architecture: he intends to physically separate performance and correctness domains in the whole system stack, from the software down to the transistors.

Dr. Wu's NSF award, which is for close to a million dollars over three years, supports his project, 3D-Integrated Intra-Chip Free-Space Optical Interconnect for Future Multi-Core SoCs, which he will pursue with co-principal investigators Distinguished Professor Eby Friedman, Professor and Associate Director of The Institute of Optics Gary Wicks, Rudolf & Hilda Kingslake Professor of Optical Engineering Duncan Moore, and Assistant Professor Huang.

According to Dr. Wu:

"Moore's Law continues to drive higher levels of system integration.
Shrinking transistor size and increasing circuit complexity make it very
difficult to transmit signals fast and reliably. In other words, the
performance of these systems has become increasingly limited by
communications between their building blocks. Future high performance
multi-core microprocessors demand a fundamental change in intra- and
inter-chip interconnect technologies. Optical interconnect is widely
accepted as the long-term solution and significant progress has been made in recent years. However, on-chip optical interconnect, which is the focus of
previous research efforts, presents some significant challenges.
Pure-optical switching and storage devices in silicon technologies remain
far from practical, and hence an optical interconnect network requires
significant overhead of repeated optical-to-electrical and then
electrical-to-optical conversions. Simultaneously, efficient silicon
electro-optic modulators remain challenging due to either large size or
small bandwidth, not to mention that both approaches require significant and expensive changes in standard silicon technologies. Both limitations will
result in unacceptable delay, circuit complexity, cost, and energy
consumption.

"This project will use free-space optics and supporting device, circuit,
packaging, and architecture level techniques to create a CMOS-compatible,
high-performance intra-chip interconnect technology. Integrated lasers,
optical phase shifters. photodetectors and focusing microlens, will be
implemented in GaAs or SiGe technologies, and 3-D integrated with CMOS
circuits underneath, which will also include the transmitter and receiver
electronics. This architecture allows point-to-point direct communication
between any two nodes, bypassing the need for routing through intermediate nodes while managing packet collisions. This project will lead to a general technology and design framework applicable to a large variety of new applications in future high performance computing and other
systems-on-chip."

-lhg