Publications
Authored books
B2. I. Vaisband, R. Jakushokas, M. Popovich, A. V. Mezhiba, S. Köse, and E. G. Friedman, On-Chip Power Delivery and Management, Fourth Edition, Springer, 2016, ISBN 978-3319293936.
B1. R. Jakushokas, M. Popovich, A. V. Mezhiba, S. Köse, and E. G. Friedman, Power Distribution Networks with On-Chip Decoupling Capacitors, Second Edition, Springer, 2011, ISBN 978-1-4419-7870-7.
B1. R. Jakushokas, M. Popovich, A. V. Mezhiba, S. Köse, and E. G. Friedman, Power Distribution Networks with On-Chip Decoupling Capacitors, Second Edition, Springer, 2011, ISBN 978-1-4419-7870-7.
Book chapters
BC2. Y. Mustafa and S. Köse, Side-channel Leakage in Suzuki Stack Circuits, Quantum Computing - Circuits, Systems, Automation and Applications,, Springer 2023, ISBN 978-3-031-37965-9.
BC2. T. Jabbari, Y. Mustafa, E. G. Friedman and S. Köse, Hardware Security of SFQ Circuits, Design Automation of Quantum Computers, Springer 2023, ISBN 78-3-031-15698-4.
BC1. L. Wang, S. Seckiner, and S. Köse, Reliability Enhanced Digital Low-Dropout Regulator with Improved Transient Performance, VLSI-SoC: New Technology Enabler, Springer 2020, ISBN 978-3-030-53272-7.
BC2. T. Jabbari, Y. Mustafa, E. G. Friedman and S. Köse, Hardware Security of SFQ Circuits, Design Automation of Quantum Computers, Springer 2023, ISBN 78-3-031-15698-4.
BC1. L. Wang, S. Seckiner, and S. Köse, Reliability Enhanced Digital Low-Dropout Regulator with Improved Transient Performance, VLSI-SoC: New Technology Enabler, Springer 2020, ISBN 978-3-030-53272-7.
Patents
P23. Z. Ignjatovic, S. Köse, and A. Y. Salim, ''CMOS Competitive System and Method for Solving Boolean Satisfiability Problems,'' US Patent Application No. 63/633,922, April 15, 2024.
P22. Z. Ignjatovic, S. Köse, and E. Elmitwalli, ''System and Method for CMOS-based Decoding,'' US Patent Application No. 63/581,787, September 11, 2023.
P21. Z. Ignjatovic, S. Köse, and E. Elmitwalli, ''CMOS-based Ising Machine with Quantized States and Current-mode Coupling,'' US Patent Application No. 63/517,750, August 4, 2023.
P20. S. Köse, L. Wang, S. K. Khatamifard, and U. R. Karpuzcu, ''Reduced Clock Pulse Width Digital Low-dropout Regulator,'' US Patent Application No. 17/410,896, February 2, 2022.
P19. S. Köse, L. Wang, S. K. Khatamifard, and U. R. Karpuzcu, ''Method and apparatus for mitigating performance degradation in digital low-dropout voltage regulators (DLDOs) caused by limit cycle oscillation (LCO) and other factors,'' US Patent 11,573,586, February 7, 2023.
P18. L. Wang, S. K. Khatamifard, U. R. Karpuzcu, and S. Köse, ''Method and apparatus for mitigating performance degradation in digital low-dropout voltage regulators (DLDOs),'' US Patent 11,493,945, November 8, 2022.
P17. B. Taskin, R. Kuttappa, and S. Köse, ''Flexible on-chip power and clock,'' US Patent 11,243,559, February 8, 2022.
P16. S. Köse, L. Wang, S. K. Khatamifard, and U. R. Karpuzcu, ''Method and apparatus for mitigating performance degradation in digital low-dropout voltage regulators (DLDOs) caused by limit cycle oscillation (LCO) and other factors,'' US Patent 11,099,591, August 24, 2021.
P15. B. Pekoz, S. Köse, and H. Arslan, ''System and method for extensionless adaptive transmitter and receiver windowing,'' US Patent 11,050,449, June 29, 2021.
P14. S. Köse and W. Yu, ''False Key-controlled Aggressive Voltage Scaling,'' US Patent 10,873,446, December 22, 2020.
P13. S. Köse and W. Yu, ''System and Method for Switched-Capacitor based Side-channel Countermeasures,'' US Patent 10,691,836, June 23, 2020.
P12. S. Köse and W. Yu, ''Security-adaptive Voltage Conversion as a Lightweight Countermeasure against LPA Attacks,'' US Patent 10,680,797, June 9, 2020.
P11. B. Pekoz, M. Hafez, S. Köse, and H. Arslan, ''Using artificial signals to maximize capacity and secrecy of multiple-input multiple-output (MIMO) communication,'' US Patent 10,644,771, May 5, 2020.
P10. B. Pekoz, Z. E. Ankarali, S. Köse, and H. Arslan, ''OFDM reception under high adjacent channel interference while preserving frame structure,'' US Patent 10,547,489, January 28, 2020.
P9. B. Pekoz, M. Hafez, S. Köse, and H. Arslan, ''Using artificial signals to maximize capacity and secrecy of multiple-input multiple-output (MIMO) communication,'' US Patent 10,516,452, December 24, 2019.
P8. B. Pekoz, S. Köse, and H. Arslan, ''Network-aware adjacent channel interference rejection and out of band emission suppression,'' US Patent 10,511,338, December 17, 2019.
P7. B. Pekoz, S. Köse, and H. Arslan, ''Combined Minimization of Intersymbol Interference (ISI) and Adjacent Channel Interference (ACI),'' US Patent 10,476,705, November 12, 2019.
P6. B. Pekoz, S. Köse, and H. Arslan, ''Combined Minimization of Intersymbol Interference (ISI) and Adjacent Channel Interference (ACI),'' US Patent 10,348,530, July 9, 2019.
P5. S. Köse and O. A. Uzun, ''Secure Converter-Gating, Reconfiguration, and Regulation,'' US Patent 9,812,954, November 7, 2017.
P4. S. Köse, O. A. Uzun, and W. Yu, ''Time Delayed Converter Reshuffling,'' US Patent 9,748,837, August 29, 2017.
P3. S. Köse and O. A. Uzun, ''System and Method for Distributed Voltage Regulator-Gating,'' US Patent 9,372,490, June 21, 2016.
P2. S. Köse and E. G. Friedman, ''Digitally Controlled Wide Range Pulse Width Modulator,'' US Patent 9,007,140, April 14, 2015.
P1. S. Köse and O. A. Uzun, ''System and Method for Voltage Regulator-Gating,'' US Patent 8,922,272, December 30, 2014.
P22. Z. Ignjatovic, S. Köse, and E. Elmitwalli, ''System and Method for CMOS-based Decoding,'' US Patent Application No. 63/581,787, September 11, 2023.
P21. Z. Ignjatovic, S. Köse, and E. Elmitwalli, ''CMOS-based Ising Machine with Quantized States and Current-mode Coupling,'' US Patent Application No. 63/517,750, August 4, 2023.
P20. S. Köse, L. Wang, S. K. Khatamifard, and U. R. Karpuzcu, ''Reduced Clock Pulse Width Digital Low-dropout Regulator,'' US Patent Application No. 17/410,896, February 2, 2022.
P19. S. Köse, L. Wang, S. K. Khatamifard, and U. R. Karpuzcu, ''Method and apparatus for mitigating performance degradation in digital low-dropout voltage regulators (DLDOs) caused by limit cycle oscillation (LCO) and other factors,'' US Patent 11,573,586, February 7, 2023.
P18. L. Wang, S. K. Khatamifard, U. R. Karpuzcu, and S. Köse, ''Method and apparatus for mitigating performance degradation in digital low-dropout voltage regulators (DLDOs),'' US Patent 11,493,945, November 8, 2022.
P17. B. Taskin, R. Kuttappa, and S. Köse, ''Flexible on-chip power and clock,'' US Patent 11,243,559, February 8, 2022.
P16. S. Köse, L. Wang, S. K. Khatamifard, and U. R. Karpuzcu, ''Method and apparatus for mitigating performance degradation in digital low-dropout voltage regulators (DLDOs) caused by limit cycle oscillation (LCO) and other factors,'' US Patent 11,099,591, August 24, 2021.
P15. B. Pekoz, S. Köse, and H. Arslan, ''System and method for extensionless adaptive transmitter and receiver windowing,'' US Patent 11,050,449, June 29, 2021.
P14. S. Köse and W. Yu, ''False Key-controlled Aggressive Voltage Scaling,'' US Patent 10,873,446, December 22, 2020.
P13. S. Köse and W. Yu, ''System and Method for Switched-Capacitor based Side-channel Countermeasures,'' US Patent 10,691,836, June 23, 2020.
P12. S. Köse and W. Yu, ''Security-adaptive Voltage Conversion as a Lightweight Countermeasure against LPA Attacks,'' US Patent 10,680,797, June 9, 2020.
P11. B. Pekoz, M. Hafez, S. Köse, and H. Arslan, ''Using artificial signals to maximize capacity and secrecy of multiple-input multiple-output (MIMO) communication,'' US Patent 10,644,771, May 5, 2020.
P10. B. Pekoz, Z. E. Ankarali, S. Köse, and H. Arslan, ''OFDM reception under high adjacent channel interference while preserving frame structure,'' US Patent 10,547,489, January 28, 2020.
P9. B. Pekoz, M. Hafez, S. Köse, and H. Arslan, ''Using artificial signals to maximize capacity and secrecy of multiple-input multiple-output (MIMO) communication,'' US Patent 10,516,452, December 24, 2019.
P8. B. Pekoz, S. Köse, and H. Arslan, ''Network-aware adjacent channel interference rejection and out of band emission suppression,'' US Patent 10,511,338, December 17, 2019.
P7. B. Pekoz, S. Köse, and H. Arslan, ''Combined Minimization of Intersymbol Interference (ISI) and Adjacent Channel Interference (ACI),'' US Patent 10,476,705, November 12, 2019.
P6. B. Pekoz, S. Köse, and H. Arslan, ''Combined Minimization of Intersymbol Interference (ISI) and Adjacent Channel Interference (ACI),'' US Patent 10,348,530, July 9, 2019.
P5. S. Köse and O. A. Uzun, ''Secure Converter-Gating, Reconfiguration, and Regulation,'' US Patent 9,812,954, November 7, 2017.
P4. S. Köse, O. A. Uzun, and W. Yu, ''Time Delayed Converter Reshuffling,'' US Patent 9,748,837, August 29, 2017.
P3. S. Köse and O. A. Uzun, ''System and Method for Distributed Voltage Regulator-Gating,'' US Patent 9,372,490, June 21, 2016.
P2. S. Köse and E. G. Friedman, ''Digitally Controlled Wide Range Pulse Width Modulator,'' US Patent 9,007,140, April 14, 2015.
P1. S. Köse and O. A. Uzun, ''System and Method for Voltage Regulator-Gating,'' US Patent 8,922,272, December 30, 2014.
Journals
J53. Y. Mustafa and S. Köse, ''Ternary Digital Output Data Link from SFQ Circuits,'' IEEE Transactions on Applied Superconductivity , Vol. , No. , pp. , (in press).
J52. K. Krause, Y. Mustafa, A. Shah, S. Köse, and M. C. Hamilton, ''Signal Integrity Simulations of 4JL Gate Pulses from 4 K to 50 K,'' IEEE Transactions on Applied Superconductivity , Vol. , No. , pp. , (in press).
J51. S. Seçkiner and S. Köse, ''A Methodology to Distribute On-Chip Voltage Regulators to Improve the Security of Hardware Masking,'' Information , Vol. 15, No. 8, pp. 1 -- 12, August 2024.
J50. Y. Mustafa, K. Krause, A. Shah, M. C. Hamilton, and S. Köse, ''DC-biased Suzuki Stack Circuit for Josephson-CMOS Memory Applications,'' Superconductor Science and Technology , Vol. 37, No. 8, pp. 085023, July 2024.
J49. Y. Mustafa and S. Köse, ''Built-in Self-test of SFQ Circuits Using Side-channel Leakage Information,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Vol. 32, No. 6, pp. 1100--1109, June 2024.
J48. W. Liu, J. Cheng, N. Sun, H. Sha, M. Jin, H. Zhao, Z. Pan, J. Wang, S. Köse, and W. Yu, ''A Low-Overhead and High-reliability Physical Unclonable Function (PUF) for Cryptography,'' Integration , Vol. 96, February 2024.
J47. N. Sun, W. Liu, J. Cheng, Z. Peng, C. Wang, C. Sun, H. Sha, Z. Pan, M. Jin, H. Zhao, J. Wang, Y. Wen, P. Kong, Y. Zhao, Y. Wang, S. Köse, and W. Yu, ''A Novel SM4 Cryptographic Architecture against Higher Order Power Analysis Attacks,'' International Journal of Circuit Theory and Applications , January 2024.
J46. E. Elmitwalli, Z. Ignjatovic, and S. Köse, ''Utilizing Multi-Body Interactions in a CMOS-Based Ising Machine for LDPC Decoding,'' IEEE Transactions on Circuits and Systems I: Regular Papers , Vol. 71, No. 1, pp. 40--50, January 2024.
J45. Y. Mustafa and S. Köse, ''Side-Channel Leakage in SFQ Circuits and Related Attacks on Qubit Control and Readout Systems,'' IEEE Transactions on Applied Superconductivity , Vol. 33, No. 6, pp. 1304307, September 2023.
J44. E. Elmitwalli and S. Köse, ''Bistable Josephson Junction based True Random Number Generator without Inductors,'' IEEE Transactions on Circuits and Systems II: Express Briefs , Vol. 70, No. 4, pp. 1615 - 1619, April 2023.
J43. Y. Mustafa and S. Köse, ''Suzuki Stack Circuit with Differential Output,'' IEEE Transactions on Applied Superconductivity , Vol. 33, No. 2, pp. 1300306, March 2023.
J42. J. Cheng, N. Sun, W. Liu, Z. Peng, C. Wang, C. Sun, Y. Wang, Y. Bi, Y. Wen, H. Zhang, P. Zhang, S. Köse, and W. Yu, ''Neural Network-Based Entropy: A New Metric for Evaluating Side-Channel Attacks,'' Journal of Circuits, Systems and Computers , Vol. 32, No. 3, February 2023.
J41. Y. Mustafa and S. Köse, ''Optimization of Suzuki Stack Circuit to Reduce Power Dissipation,'' IEEE Transactions on Applied Superconductivity , Vol. 32, No. 8, pp. 1 - 7, November 2022.
J40. S. Seçkiner and S. Köse, ''Exploiting On-chip Voltage Regulators for Leakage Reduction in Hardware Masking,'' Sensors , Vol. 22, No. 18, pp. 1 -- 25, September 2022.
J39. E. Elmitwalli, K. Ni, and S. Köse, ''Machine Learning Attack Resistant Area-Efficient Reconfigurable Ising-PUF,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Vol. 30, No. 4, pp. 526 - 538, April 2022.
J38. Y. Mustafa, T. Jabbari, and S. Köse, ''Emerging Attacks on Logic Locking in SFQ Circuits and Related Countermeasures,'' IEEE Transactions on Applied Superconductivity , Vol. 32, No. 3, pp. 1 - 8, March 2022.
J37. S. Seçkiner and S. Köse, ''Preprocessing of the Physical Leakage Information to Combine Side-Channel Distinguishers,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Vol. 29, No. 12, pp. 2052 - 2063, December 2021.
J36. E. Elmitwalli, K. Ni, and S. Köse, ''A PVT Tolerant True Random Number Generator based on Oscillator Phase under Sub-Harmonic Injection Locking,'' IEEE Access , Vol. 9, pp. 141626 - 141634, October 2021.
J35. F. Amsaad, A. Oun, M. Y. Niamat, A. Razaque, S. Köse, M. Mahmoud, W. Alasmary, and F. Alsolami, ''Enhancing the Performance of Lightweight Configurable PUF for Robust IoT Hardware-Assisted Security,'' IEEE Access , Vol. 9, No. , pp. 136792 -- 136810, October 2021.
J34. F. Amsaad and S. Köse, ''A Secure Lightweight Hardware-assisted Charging Coordination Authentication Framework for Trusted Smart Grid Energy Storage Units,'' Springer Nature - Computer Science , pp. 1 -- 15, September 2021.
J33. F. Amsaad and S. Köse, ''A Secure Hardware-Assisted AMI Authentication Scheme for Smart Cities,'' IEEE Consumer Electronics Magazine , Vol. 10, No. 4, pp. 106 -- 112, July 2021.
J32. B. Pekoz, Z. E. Ankarali, S. Köse, and H. Arslan ''Reducing Precoder/Channel Mismatch and Enhancing Secrecy in Practical MIMO Systems Using Artificial Signals,'' IEEE Communication Letters , Vol. 24, No. 6, pp. 1347 -- 1350, June 2020.
J31. B. Pekoz, S. Köse, and H. Arslan ''Extensionless Adaptive Transmitter and Receiver Windowing of Beyond 5G Frames,'' IEEE Transactions on Vehicular Technology , Vol. 69, No. 2, pp. 1888 -- 1902, February 2020.
J30. B. Pekoz, Z. E. Ankarali, S. Köse, and H. Arslan ''Non-Redundant OFDM Receiver Windowing for 5G Frames & Beyond,'' IEEE Transactions on Vehicular Technology , Vol. 69, No. 1, pp. 676 -- 684, January 2020.
J29. R. Kuttappa, S. Köse, and B. Taskin ''FOPAC: Flexible On-Chip Power and Clock,'' IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 66, No. 12, pp. 4628 -- 4636, December 2019.
J28. F. Demir, B. Pekoz, S. Köse, and H. Arslan ''An Innovative Telecommunications Training Through Flexible Radio Platforms,'' IEEE Communication Magazine, Vol. 57, No. 11, pp. 27 -- 33, November 2019.
J27. L. Wang, S. K. Khatamifard, U. R. Karpuzcu, and S. Köse, ''Exploring On-Chip Power Delivery Network Induced Analog Covert Channels,'' IEEE TC on Cyber-Physical Systems Newsletter, Vol. 4, No. 1, pp. 15 -- 18, February 2019.
J26. L. Wang, S. K. Khatamifard, U. R. Karpuzcu, and S. Köse, ''Exploiting Algorithmic Noise Tolerance for Scalable On-Chip Voltage Regulation,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 27, No. 1, pp. 229 -- 242, January 2019.
J25. S. K. Khatamifard, L. Wang, S. Köse, and U. R. Karpuzcu, ''A New Class of Covert Channels Exploiting Power Management Vulnerabilities,'' IEEE Computer Architecture Letters, Vol. 17, No. 2, pp. 201 -- 204, July-December 2018.
J24. W. Yu, Y. Chen, S. Köse, and J. Chen, ''Exploiting Multi-Phase On-Chip Voltage Regulators as Strong PUF Primitives for Securing IoT,'' Journal of Electronic Testing, Vol. 34, No. 5, pp. 587 -- 598, October 2018.
J23. M. Azhar, F. Amsaad, and S. Köse, ''Duty Cycle-based Controlled Physical Unclonable Function,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 26, No. 9, pp. 1647 -- 1658, September 2018.
J22. F. Amsaad, M. Niamat, A. Dawoud, and S. Köse, ''Reliable Delay based Algorithm to Boost PUF Security against Modeling Attacks,'' Information, Vol. 9, No. 9, pp. 1 -- 15, September 2018.
J21. W. Yu and S. Köse, ''Exploiting Voltage Regulators to Enhance Various Power Attack Countermeasures,'' IEEE Transactions on Emerging Topics in Computing, Vol. 6, No. 2, pp. 244 -- 257, April-June 2018.
J20. S. A. Sadat, M. Canbolat, and S. Köse, ''Optimal Allocation of LDOs and Decoupling Capacitors within a Distributed On-Chip Power Grid,'' ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol 23, No. 4, pp. 49:1 -- 49:15, May 2018.
J19. M. Yilmaz, E. Guvenkaya, H. M. Furqan, S. Köse, and H. Arslan, ''Cognitive Security of Wireless Communication Systems in the Physical Layer,'' Wireless Communications and Mobile Computing, Vol. 2017, pp. 1 -- 9, December 2017.
J18. M. Yilmaz, S. Köse, N. Chamok, M. Ali, and H. Arslan, ''Partially Overlapping Filtered Multitone with Reconfigurable Antennas in Uncoordinated Networks,'' Physical Communication, Vol. 25, No. 1, pp. 249 -- 258, December 2017.
J17. W. Yu and S. Köse, ''False Key-Controlled Aggressive Voltage Scaling: A Countermeasure Against LPA Attacks,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 36, No. 12, pp. 2149 -- 2153, December 2017.
J16. L. Wang, S. K. Khatamifard, O. A. Uzun, U. R. Karpuzcu, and S. Köse, ''Efficiency, Stability, and Reliability Implications of Unbalanced Current Sharing among Distributed On-Chip Voltage Regulators,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, No. 11, pp. 3019 -- 3032, November 2017.
J15. W. Yu and S. Köse, ''A Lightweight Masked AES Implementation for Securing IoT Against CPA Attacks,'' IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 64, No. 11, pp. 2934 -- 2944, November 2017.
J14. W. Yu and S. Köse, ''Security-Adaptive Voltage Conversion as a Lightweight Countermeasure Against LPA Attacks,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, No. 7, pp. 2183 -- 2187, July 2017.
J13. W. Yu and S. Köse, ''A Voltage Regulator-Assisted Lightweight AES Implementation Against DPA Attacks,'' IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 63, No. 8, pp. 1152 - 1163, August 2016.
J12. W. Yu and S. Köse, ''Charge-Withheld Converter-Reshuffling (CoRe): A Countermeasure Against Power Analysis Attacks,'' IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 63, No. 5, pp. 438 - 442, May 2016.
J11. W. Yu and S. Köse, ''Security Implications of Simultaneous Dynamic and Leakage Power Analysis Attacks on Nanoscale Cryptographic Circuits,'' IET Electronics Letters, Vol.52, Issue 6, pp. 466 - 468, March 2016.
J10. W. Yu and S. Köse, ''Time-Delayed Converter-Reshuffling: An Efficient and Secure Power Delivery Architecture,'' IEEE Embedded Systems Letters, Vol. 7, No. 3, pp. 73 - 76, September 2015.
J9. I. Vaisband, B. Price, S. Köse, Y. Kolla, E. G. Friedman, and J. Fischer, ''Distributed Power Delivery with 28 nm Ultra-Small LDO Regulator,'' Analog Integrated Circuits and Signal Processing, Vol. 83, Issue 3, pp. 295 - 309, 2015.
J8. I. Vaisband, M. Azhar, E. G. Friedman, and S. Köse, ''Digitally Controlled Pulse Width Modulator for On-Chip Power Management,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 12, pp. 2527 - 2534, December 2014.
J7. O. A. Uzun and S. Köse, ''Converter-Gating: A Power Efficient and Secure On-Chip Power Delivery System,'' IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 4, No. 2, pp. 169 - 179, June 2014.
J6. S. Köse, S. Tam, S. Pinzon, B. McDermott, and E. G. Friedman, ''Active Filter Based Hybrid On-Chip DC-DC Converters for Point-of-Load Voltage Regulation,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 4, pp. 680 - 691, April 2013.
J5. I. Savidis, S. Köse, and E. G. Friedman, ''Power Noise in TSV-based 3-D Integrated Circuits,'' IEEE Journal of Solid-State Circuits, Vol. 48, No. 2, pp. 587 - 597, February 2013.
J4. S. Köse and E. G. Friedman, ''Distributed On-Chip Power Delivery,'' IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 2, No. 4, pp. 704 - 713, December 2012.
J3. S. Köse and E. G. Friedman, ''Efficient Algorithms for Fast IR Drop Analysis Exploiting Locality,'' Integration, the VLSI Journal, Vol. 45, No. 2, pp. 149 - 161, March 2012.
J2. S. Köse and E. G. Friedman, ''Effective Resistance of a Two Layer Mesh,'' IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 58, No. 11, pp. 739 - 743, November 2011.
J1. S. Köse, E. Salman, and E. G. Friedman, ''Shielding Methodologies in the Presence of Power/Ground Noise,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 8, pp. 1458 - 1468, August 2011.
J52. K. Krause, Y. Mustafa, A. Shah, S. Köse, and M. C. Hamilton, ''Signal Integrity Simulations of 4JL Gate Pulses from 4 K to 50 K,'' IEEE Transactions on Applied Superconductivity , Vol. , No. , pp. , (in press).
J51. S. Seçkiner and S. Köse, ''A Methodology to Distribute On-Chip Voltage Regulators to Improve the Security of Hardware Masking,'' Information , Vol. 15, No. 8, pp. 1 -- 12, August 2024.
J50. Y. Mustafa, K. Krause, A. Shah, M. C. Hamilton, and S. Köse, ''DC-biased Suzuki Stack Circuit for Josephson-CMOS Memory Applications,'' Superconductor Science and Technology , Vol. 37, No. 8, pp. 085023, July 2024.
J49. Y. Mustafa and S. Köse, ''Built-in Self-test of SFQ Circuits Using Side-channel Leakage Information,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Vol. 32, No. 6, pp. 1100--1109, June 2024.
J48. W. Liu, J. Cheng, N. Sun, H. Sha, M. Jin, H. Zhao, Z. Pan, J. Wang, S. Köse, and W. Yu, ''A Low-Overhead and High-reliability Physical Unclonable Function (PUF) for Cryptography,'' Integration , Vol. 96, February 2024.
J47. N. Sun, W. Liu, J. Cheng, Z. Peng, C. Wang, C. Sun, H. Sha, Z. Pan, M. Jin, H. Zhao, J. Wang, Y. Wen, P. Kong, Y. Zhao, Y. Wang, S. Köse, and W. Yu, ''A Novel SM4 Cryptographic Architecture against Higher Order Power Analysis Attacks,'' International Journal of Circuit Theory and Applications , January 2024.
J46. E. Elmitwalli, Z. Ignjatovic, and S. Köse, ''Utilizing Multi-Body Interactions in a CMOS-Based Ising Machine for LDPC Decoding,'' IEEE Transactions on Circuits and Systems I: Regular Papers , Vol. 71, No. 1, pp. 40--50, January 2024.
J45. Y. Mustafa and S. Köse, ''Side-Channel Leakage in SFQ Circuits and Related Attacks on Qubit Control and Readout Systems,'' IEEE Transactions on Applied Superconductivity , Vol. 33, No. 6, pp. 1304307, September 2023.
J44. E. Elmitwalli and S. Köse, ''Bistable Josephson Junction based True Random Number Generator without Inductors,'' IEEE Transactions on Circuits and Systems II: Express Briefs , Vol. 70, No. 4, pp. 1615 - 1619, April 2023.
J43. Y. Mustafa and S. Köse, ''Suzuki Stack Circuit with Differential Output,'' IEEE Transactions on Applied Superconductivity , Vol. 33, No. 2, pp. 1300306, March 2023.
J42. J. Cheng, N. Sun, W. Liu, Z. Peng, C. Wang, C. Sun, Y. Wang, Y. Bi, Y. Wen, H. Zhang, P. Zhang, S. Köse, and W. Yu, ''Neural Network-Based Entropy: A New Metric for Evaluating Side-Channel Attacks,'' Journal of Circuits, Systems and Computers , Vol. 32, No. 3, February 2023.
J41. Y. Mustafa and S. Köse, ''Optimization of Suzuki Stack Circuit to Reduce Power Dissipation,'' IEEE Transactions on Applied Superconductivity , Vol. 32, No. 8, pp. 1 - 7, November 2022.
J40. S. Seçkiner and S. Köse, ''Exploiting On-chip Voltage Regulators for Leakage Reduction in Hardware Masking,'' Sensors , Vol. 22, No. 18, pp. 1 -- 25, September 2022.
J39. E. Elmitwalli, K. Ni, and S. Köse, ''Machine Learning Attack Resistant Area-Efficient Reconfigurable Ising-PUF,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Vol. 30, No. 4, pp. 526 - 538, April 2022.
J38. Y. Mustafa, T. Jabbari, and S. Köse, ''Emerging Attacks on Logic Locking in SFQ Circuits and Related Countermeasures,'' IEEE Transactions on Applied Superconductivity , Vol. 32, No. 3, pp. 1 - 8, March 2022.
J37. S. Seçkiner and S. Köse, ''Preprocessing of the Physical Leakage Information to Combine Side-Channel Distinguishers,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Vol. 29, No. 12, pp. 2052 - 2063, December 2021.
J36. E. Elmitwalli, K. Ni, and S. Köse, ''A PVT Tolerant True Random Number Generator based on Oscillator Phase under Sub-Harmonic Injection Locking,'' IEEE Access , Vol. 9, pp. 141626 - 141634, October 2021.
J35. F. Amsaad, A. Oun, M. Y. Niamat, A. Razaque, S. Köse, M. Mahmoud, W. Alasmary, and F. Alsolami, ''Enhancing the Performance of Lightweight Configurable PUF for Robust IoT Hardware-Assisted Security,'' IEEE Access , Vol. 9, No. , pp. 136792 -- 136810, October 2021.
J34. F. Amsaad and S. Köse, ''A Secure Lightweight Hardware-assisted Charging Coordination Authentication Framework for Trusted Smart Grid Energy Storage Units,'' Springer Nature - Computer Science , pp. 1 -- 15, September 2021.
J33. F. Amsaad and S. Köse, ''A Secure Hardware-Assisted AMI Authentication Scheme for Smart Cities,'' IEEE Consumer Electronics Magazine , Vol. 10, No. 4, pp. 106 -- 112, July 2021.
J32. B. Pekoz, Z. E. Ankarali, S. Köse, and H. Arslan ''Reducing Precoder/Channel Mismatch and Enhancing Secrecy in Practical MIMO Systems Using Artificial Signals,'' IEEE Communication Letters , Vol. 24, No. 6, pp. 1347 -- 1350, June 2020.
J31. B. Pekoz, S. Köse, and H. Arslan ''Extensionless Adaptive Transmitter and Receiver Windowing of Beyond 5G Frames,'' IEEE Transactions on Vehicular Technology , Vol. 69, No. 2, pp. 1888 -- 1902, February 2020.
J30. B. Pekoz, Z. E. Ankarali, S. Köse, and H. Arslan ''Non-Redundant OFDM Receiver Windowing for 5G Frames & Beyond,'' IEEE Transactions on Vehicular Technology , Vol. 69, No. 1, pp. 676 -- 684, January 2020.
J29. R. Kuttappa, S. Köse, and B. Taskin ''FOPAC: Flexible On-Chip Power and Clock,'' IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 66, No. 12, pp. 4628 -- 4636, December 2019.
J28. F. Demir, B. Pekoz, S. Köse, and H. Arslan ''An Innovative Telecommunications Training Through Flexible Radio Platforms,'' IEEE Communication Magazine, Vol. 57, No. 11, pp. 27 -- 33, November 2019.
J27. L. Wang, S. K. Khatamifard, U. R. Karpuzcu, and S. Köse, ''Exploring On-Chip Power Delivery Network Induced Analog Covert Channels,'' IEEE TC on Cyber-Physical Systems Newsletter, Vol. 4, No. 1, pp. 15 -- 18, February 2019.
J26. L. Wang, S. K. Khatamifard, U. R. Karpuzcu, and S. Köse, ''Exploiting Algorithmic Noise Tolerance for Scalable On-Chip Voltage Regulation,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 27, No. 1, pp. 229 -- 242, January 2019.
J25. S. K. Khatamifard, L. Wang, S. Köse, and U. R. Karpuzcu, ''A New Class of Covert Channels Exploiting Power Management Vulnerabilities,'' IEEE Computer Architecture Letters, Vol. 17, No. 2, pp. 201 -- 204, July-December 2018.
J24. W. Yu, Y. Chen, S. Köse, and J. Chen, ''Exploiting Multi-Phase On-Chip Voltage Regulators as Strong PUF Primitives for Securing IoT,'' Journal of Electronic Testing, Vol. 34, No. 5, pp. 587 -- 598, October 2018.
J23. M. Azhar, F. Amsaad, and S. Köse, ''Duty Cycle-based Controlled Physical Unclonable Function,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 26, No. 9, pp. 1647 -- 1658, September 2018.
J22. F. Amsaad, M. Niamat, A. Dawoud, and S. Köse, ''Reliable Delay based Algorithm to Boost PUF Security against Modeling Attacks,'' Information, Vol. 9, No. 9, pp. 1 -- 15, September 2018.
J21. W. Yu and S. Köse, ''Exploiting Voltage Regulators to Enhance Various Power Attack Countermeasures,'' IEEE Transactions on Emerging Topics in Computing, Vol. 6, No. 2, pp. 244 -- 257, April-June 2018.
J20. S. A. Sadat, M. Canbolat, and S. Köse, ''Optimal Allocation of LDOs and Decoupling Capacitors within a Distributed On-Chip Power Grid,'' ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol 23, No. 4, pp. 49:1 -- 49:15, May 2018.
J19. M. Yilmaz, E. Guvenkaya, H. M. Furqan, S. Köse, and H. Arslan, ''Cognitive Security of Wireless Communication Systems in the Physical Layer,'' Wireless Communications and Mobile Computing, Vol. 2017, pp. 1 -- 9, December 2017.
J18. M. Yilmaz, S. Köse, N. Chamok, M. Ali, and H. Arslan, ''Partially Overlapping Filtered Multitone with Reconfigurable Antennas in Uncoordinated Networks,'' Physical Communication, Vol. 25, No. 1, pp. 249 -- 258, December 2017.
J17. W. Yu and S. Köse, ''False Key-Controlled Aggressive Voltage Scaling: A Countermeasure Against LPA Attacks,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 36, No. 12, pp. 2149 -- 2153, December 2017.
J16. L. Wang, S. K. Khatamifard, O. A. Uzun, U. R. Karpuzcu, and S. Köse, ''Efficiency, Stability, and Reliability Implications of Unbalanced Current Sharing among Distributed On-Chip Voltage Regulators,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, No. 11, pp. 3019 -- 3032, November 2017.
J15. W. Yu and S. Köse, ''A Lightweight Masked AES Implementation for Securing IoT Against CPA Attacks,'' IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 64, No. 11, pp. 2934 -- 2944, November 2017.
J14. W. Yu and S. Köse, ''Security-Adaptive Voltage Conversion as a Lightweight Countermeasure Against LPA Attacks,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, No. 7, pp. 2183 -- 2187, July 2017.
J13. W. Yu and S. Köse, ''A Voltage Regulator-Assisted Lightweight AES Implementation Against DPA Attacks,'' IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 63, No. 8, pp. 1152 - 1163, August 2016.
J12. W. Yu and S. Köse, ''Charge-Withheld Converter-Reshuffling (CoRe): A Countermeasure Against Power Analysis Attacks,'' IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 63, No. 5, pp. 438 - 442, May 2016.
J11. W. Yu and S. Köse, ''Security Implications of Simultaneous Dynamic and Leakage Power Analysis Attacks on Nanoscale Cryptographic Circuits,'' IET Electronics Letters, Vol.52, Issue 6, pp. 466 - 468, March 2016.
J10. W. Yu and S. Köse, ''Time-Delayed Converter-Reshuffling: An Efficient and Secure Power Delivery Architecture,'' IEEE Embedded Systems Letters, Vol. 7, No. 3, pp. 73 - 76, September 2015.
J9. I. Vaisband, B. Price, S. Köse, Y. Kolla, E. G. Friedman, and J. Fischer, ''Distributed Power Delivery with 28 nm Ultra-Small LDO Regulator,'' Analog Integrated Circuits and Signal Processing, Vol. 83, Issue 3, pp. 295 - 309, 2015.
J8. I. Vaisband, M. Azhar, E. G. Friedman, and S. Köse, ''Digitally Controlled Pulse Width Modulator for On-Chip Power Management,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 12, pp. 2527 - 2534, December 2014.
J7. O. A. Uzun and S. Köse, ''Converter-Gating: A Power Efficient and Secure On-Chip Power Delivery System,'' IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 4, No. 2, pp. 169 - 179, June 2014.
J6. S. Köse, S. Tam, S. Pinzon, B. McDermott, and E. G. Friedman, ''Active Filter Based Hybrid On-Chip DC-DC Converters for Point-of-Load Voltage Regulation,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 4, pp. 680 - 691, April 2013.
J5. I. Savidis, S. Köse, and E. G. Friedman, ''Power Noise in TSV-based 3-D Integrated Circuits,'' IEEE Journal of Solid-State Circuits, Vol. 48, No. 2, pp. 587 - 597, February 2013.
J4. S. Köse and E. G. Friedman, ''Distributed On-Chip Power Delivery,'' IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 2, No. 4, pp. 704 - 713, December 2012.
J3. S. Köse and E. G. Friedman, ''Efficient Algorithms for Fast IR Drop Analysis Exploiting Locality,'' Integration, the VLSI Journal, Vol. 45, No. 2, pp. 149 - 161, March 2012.
J2. S. Köse and E. G. Friedman, ''Effective Resistance of a Two Layer Mesh,'' IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 58, No. 11, pp. 739 - 743, November 2011.
J1. S. Köse, E. Salman, and E. G. Friedman, ''Shielding Methodologies in the Presence of Power/Ground Noise,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 8, pp. 1458 - 1468, August 2011.
Conferences
C57. I. Dagli, J. Crea, S. Seckiner, Y. Xu, S. Köse and Mehmet E. Belviranli, "MC3: Contention-based Covert Channels Exploiting Shared DRAM Vulnerabilities on System-on-Chips,"Proceedings of the IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE), March 2025.
C56. Y. Mustafa and S. Köse, "Side-Channel Attacks Targeting Classical-Quantum Interface in Quantum Computers," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2024.
C55. Y. Mustafa and S. Köse, "Side-Channel Leakage in Superconductive Electronics: Foe or Friend?," IEEE Microelectronics Design and Test Symposium (MDTS), May 2024.
C54. Y. Mustafa and S. Köse, "Covert Communication Attacks in Chiplet-based 2.5-D Integration Systems," IEEE International System-on-Chip Conference (SOCC), September 2023.
C53. Y. Mustafa and S. Köse, "Modeling and Analysis of Switched-Capacitor Converters as a Multi-port Network for Covert Communication," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), June 2023.
C52. S. Seçkiner and S. Köse, "Security Implications of Decoupling Capacitors on Leakage Reduction in Hardware Masking," Proceedings of the IEEE Latin America Symposium on Circuits and Systems (LASCAS), March 2023.
C51. Y. Mustafa and S. Köse, "Side-channel Leakage in Suzuki Stack Circuits," International Symposium on Quantum Computing: Circuits Systems Automation and Applications (QC-CSAA), July 2022.
C50. S. Seçkiner and S. Köse, "Combined Side-Channel Attacks on a Lightweight Prince Cipher Implementation," Proceedings of the IEEE International SoC Conference, September 2021.
C49. F. Amsaad and S. Köse, "A Lightweight Hardware-Based Authentication for Secure Smart Grid Energy Storage Units," IEEE World Forum of Internet of Things (WF-IoT), June 2021.
C48. F. Amsaad, A. Razaque, M. Baza, S. Köse, S. Bhatia, and G. Srivastava, "An Efficient and Reliable Lightweight PUF for IoT-based Applications," IEEE International Conference on Communications Workshops, pp. 1 - 6, June 2021.
C47. H. Dai and S. Köse, "On the Vulnerability of Hardware Masking in Practical Implementations," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), June 2021.
C46. S. Seckiner and S. Köse, "Combined Distinguishers to Improve the Preprocessing Efficiency of Physical Leakage Measurements in Side-channel Attacks," Government Microcircuit Applications and Critical Technology Conference, March 2021.
C45. L. Wang and S. Köse, "Startup Aware Reliability Enhancement Controller for On-Chip Digital LDOs," Government Microcircuit Applications and Critical Technology Conference, March 2021.
C44. L. Wang and S. Köse, "Approximate Voltage Regulation for Energy Efficient Error Tolerable Applications," IEEE International Midwest Symposium on Circuits and Systems, pp. 726-729, August 2020.
C43. A. Khanna, E. Elmitwalli, S. Dutta, S. Deng, S. Datta, S. Köse, and K. Ni, "A Bias and Correlation Free True Random Number Generator Based on Quantized Oscillator Phase under Sub-Harmonic Injection Locking," Symposia on VLSI Technology and Circuits, June 2020.
C42. F. Amsaad and S. Köse, "A Trusted Authentication Scheme for IoT-Based Smart Grid Applications," IEEE World Forum of Internet of Things (WF-IoT), pp. 1 -- 6, June 2019.
C41. S. Seckiner, L. Wang, and S. Köse, "An NBTI-Aware Digital Low-Dropout Regulator with Adaptive Gain Scaling Control," IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 191 -- 196, October 2019.
C40. L. Wang, R. Kuttappa, B. Taskin, and S. Köse, "Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation," Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), June 2019.
C39. M. A. Vosoughi, L. Wang, and S. Köse, "Bus-Invert Coding as a Low-Power Countermeasure Against Correlation Power Analysis Attack," Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), June 2019.
C38. M. A. Vosoughi and S. Köse, "Combined Distinguishers to Enhance the Accuracy and Success of Side Channel Analysis," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2019.
C37. M. A. Vosoughi and S. Köse, "Leveraging On-Chip Voltage Regulators Against Fault Injection Attacks," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), May 2019.
C36. L. Wang and S. Köse, "Reliability Enhanced On-Chip Digital LDO with Limit Cycle Oscillation Mitigation," Government Microcircuit Applications and Critical Technology Conference, March 2019.
C35. S. K. Khatamifard, L. Wang, S. Köse, and U. R. Karpuzcu, "POWERT Channels: A Novel Class of Covert Communication Exploiting Power Management Vulnerabilities," Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA), pp. 291 - 303, February 2019.
C34. L. Wang and S. Köse, "When Hardware Security Moves to the Edge and Fog," Proceedings of the IEEE International Conference on Digital Signal Processing (DSP'18), November 2018.
C33. M. Azhar and S. Köse, "Process, Voltage, and Temperature-stable Adaptive Duty Cycle based PUF," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1 - 5, May 2018.
C32. L. Wang and S. Köse, "Reliable On-Chip Voltage Regulation for Sustainable and Compact IoT and Heterogeneous Computing Systems," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. ?? - ??, May 2018.
C31. L. Wang, S. K. Khatamifard, U. R. Karpuzcu, and S. Köse, "Mitigation of NBTI Induced Performance Degradation in On-Chip Digital LDOs,"Proceedings of the IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 803 - 808, March 2018.
C30. A. W. Khan, T. Wanchoo, G. Mumcu, and S. Köse, "Implications of Distributed On-Chip Power Delivery on EM Side-Channel Attacks," IEEE International Conference on Computer Design (ICCD), pp. 329 - 336, November 2017.
C29. B. Pekoz, S. Köse, and H. Arslan, "Adaptive Windowing of Insufficient CP for Joint Minimization of ISI and ACI Beyond 5G," IEEE Annual International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC) , pp. 1 - 5, October 2017.
C28. A. Roohi, R. Demara, L. Wang, and S. Köse, "Secure Intermittent-Robust Computation for Energy Harvesting Device Security and Outage Resilience," IEEE Conference on Advanced and Trusted Computing, pp. 1 - 6, August 2017.
C27. S. K. Khatamifard, L. Wang, W. Yu, S. Köse, and U. R. Karpuzcu, "ThermoGater: Thermally-Aware On-Chip Voltage Regulation," Proceedings of the IEEE International Symposium on Computer Architecture (ISCA), pp. 120 - 132, June 2017.
C26. W. Yu and S. Köse, "A Lightweight AES Implementation Against Bivariate First-Order DPA Attacks," Proceedings of the ACM Workshop on Hardware and Architectural Support for Security and Privacy (HASP), pp. 1 - 7, June 2017.
C25. S. Köse, "Efficient and Secure On-Chip Reconfigurable Voltage Regulation for IoT Devices," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 369 - 374, May 2017.
C24. V. T. Alaparthy and S. Köse, "An Adaptive Senior Design Course with an Emphasis on Undergraduate Course Curriculum," Proceedings of the IEEE International Conference on Microelectronics System Education, pp. 59 - 62, May 2017.
C23. W. Yu and S. Köse, "Implications of Noise Insertion Mechanisms of Different Countermeasures Against Side-Channel Attacks," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. ?? - ??, May 2017.
C22. S. Köse, L. Wang, and R. Demara, "On-Chip Sensor Circle Distribution Technique for Real-Time Hardware Trojan Detection," Government Microcircuit Applications and Critical Technology Conference, March 2017.
C21. W. Yu, O. A. Uzun, and S. Köse, "Leveraging On-Chip Voltage Regulators as a Countermeasure Against Side-Channel Attacks," Proceedings of the IEEE/ACM Design Automation Conference (DAC), pp. 1 - 6, June 2015.
C20. M. E. Belviranli, W. Yu, and S. Köse, "Ultra-Fine Grain Power Management at Datapath-Level: Fact or Fiction," International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) WACI Session, March 2015.
C19. O. A. Uzun and S. Köse, "Regulator-Gating Methodology With Distributed Switched Capacitor Voltage Converters," Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pp. 13 - 18, July 2014.
C18. S. Köse, "Thermal Implications of On-Chip Voltage Regulation: Upcoming Challenges and Possible Solutions," Proceedings of the IEEE/ACM Design Automation Conference (DAC), pp. 1 - 6, June 2014.
C17. M. Azhar and S. Köse, "An Enhanced Pulse Width Modulator with Adaptive Duty Cycle and Frequency Control," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 958 - 961, June 2014.
C16. S. Köse, "Regulator-Gating: Adaptive Management of On-Chip Voltage Regulators," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 105 - 110, May 2014.
C15. S. Köse, I. Vaisband, and E. G. Friedman, "Digitally Controlled Wide Range Pulse Width Modulator for On-Chip Power Supplies," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2251 - 2254, May 2013.
C14. S. Köse, E. G. Friedman, R. M. Secareanu, and O. Hartin, "Current Profile of a Microcontroller to Determine Electromagnetic Emissions," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2650 - 2653, May 2013.
C13. S. Köse and E. G. Friedman, "Distributed Power Delivery for Energy Efficient and Low Power Systems," Asilomar Conference on Signals, Systems, and Computers, pp. 757 - 761, November 2012.
C12. S. Köse and E. G. Friedman, "Design Methodology to Distribute On-Chip Power in Next Generation Integrated Circuits," IEEE 27th Convention of Electrical and Electronics Engineers in Israel, pp. 1 - 4, November 2012.
C11. S. Köse and E. G. Friedman, "Power Delivery in Heterogeneous Integrated Circuits," IEEE CAS-FEST Workshop (in conjunction with ISCAS2012), May 2012.
C10. S. Köse, S. Tam, S. Pinzon, B. McDermott, and E. G. Friedman, "An Area Efficient On-Chip Hybrid Voltage Regulator," Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), pp. 398-403, March 2012.
C9. S. Köse and E. G. Friedman, "Fast Algorithms for IR Voltage Drop Analysis Exploiting Locality," Proceedings of the IEEE/ACM Design Automation Conference (DAC), pp. 996-1001, June 2011.
C8. S. Köse and E. G. Friedman, "Distributed Power Network Co-Design with On-Chip Power Supplies and Decoupling Capacitors," Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), June 2011.
C7. I. Savidis, S. Köse, and E. G. Friedman, "Power Grid Noise in TSV-Based 3-D Integrated Systems," Government Microcircuit Applications and Critical Technology Conference, March 2011.
C6. S. Köse and E. G. Friedman, "Simultaneous Co-Design of Distributed On-Chip Power Supplies and Decoupling Capacitors," Proceedings of the IEEE International SoC Conference, pp. 15 - 18, September 2010.
C5. S. Köse and E. G. Friedman, "An Area Efficient Fully Monolithic Hybrid Voltage Regulator," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2718 - 2721, May/June 2010.
C4. S. Köse and E. G. Friedman, "Fast Algorithms for Power Grid Analysis Based on Effective Resistance," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 3661 - 3664, May/June 2010.
C3. S. Köse and E. G. Friedman, "On-Chip Point-of-Load Voltage Regulator for Distributed Power Supplies," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 377 - 380, May 2010.
C2. S. Köse, E. Salman, and E. G. Friedman, "Shielding Methodologies in the Presence of Power/Ground Noise," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2277 - 2280, May 2009.
C1. S. Köse, E. Salman, Z. Ignjatovic, and E. G. Friedman, "Pseudo-Random Clocking to Enhance Signal Integrity," Proceedings of the IEEE International SoC Conference, pp. 47-50, September 2008.
C56. Y. Mustafa and S. Köse, "Side-Channel Attacks Targeting Classical-Quantum Interface in Quantum Computers," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2024.
C55. Y. Mustafa and S. Köse, "Side-Channel Leakage in Superconductive Electronics: Foe or Friend?," IEEE Microelectronics Design and Test Symposium (MDTS), May 2024.
C54. Y. Mustafa and S. Köse, "Covert Communication Attacks in Chiplet-based 2.5-D Integration Systems," IEEE International System-on-Chip Conference (SOCC), September 2023.
C53. Y. Mustafa and S. Köse, "Modeling and Analysis of Switched-Capacitor Converters as a Multi-port Network for Covert Communication," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), June 2023.
C52. S. Seçkiner and S. Köse, "Security Implications of Decoupling Capacitors on Leakage Reduction in Hardware Masking," Proceedings of the IEEE Latin America Symposium on Circuits and Systems (LASCAS), March 2023.
C51. Y. Mustafa and S. Köse, "Side-channel Leakage in Suzuki Stack Circuits," International Symposium on Quantum Computing: Circuits Systems Automation and Applications (QC-CSAA), July 2022.
C50. S. Seçkiner and S. Köse, "Combined Side-Channel Attacks on a Lightweight Prince Cipher Implementation," Proceedings of the IEEE International SoC Conference, September 2021.
C49. F. Amsaad and S. Köse, "A Lightweight Hardware-Based Authentication for Secure Smart Grid Energy Storage Units," IEEE World Forum of Internet of Things (WF-IoT), June 2021.
C48. F. Amsaad, A. Razaque, M. Baza, S. Köse, S. Bhatia, and G. Srivastava, "An Efficient and Reliable Lightweight PUF for IoT-based Applications," IEEE International Conference on Communications Workshops, pp. 1 - 6, June 2021.
C47. H. Dai and S. Köse, "On the Vulnerability of Hardware Masking in Practical Implementations," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), June 2021.
C46. S. Seckiner and S. Köse, "Combined Distinguishers to Improve the Preprocessing Efficiency of Physical Leakage Measurements in Side-channel Attacks," Government Microcircuit Applications and Critical Technology Conference, March 2021.
C45. L. Wang and S. Köse, "Startup Aware Reliability Enhancement Controller for On-Chip Digital LDOs," Government Microcircuit Applications and Critical Technology Conference, March 2021.
C44. L. Wang and S. Köse, "Approximate Voltage Regulation for Energy Efficient Error Tolerable Applications," IEEE International Midwest Symposium on Circuits and Systems, pp. 726-729, August 2020.
C43. A. Khanna, E. Elmitwalli, S. Dutta, S. Deng, S. Datta, S. Köse, and K. Ni, "A Bias and Correlation Free True Random Number Generator Based on Quantized Oscillator Phase under Sub-Harmonic Injection Locking," Symposia on VLSI Technology and Circuits, June 2020.
C42. F. Amsaad and S. Köse, "A Trusted Authentication Scheme for IoT-Based Smart Grid Applications," IEEE World Forum of Internet of Things (WF-IoT), pp. 1 -- 6, June 2019.
C41. S. Seckiner, L. Wang, and S. Köse, "An NBTI-Aware Digital Low-Dropout Regulator with Adaptive Gain Scaling Control," IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 191 -- 196, October 2019.
C40. L. Wang, R. Kuttappa, B. Taskin, and S. Köse, "Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation," Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), June 2019.
C39. M. A. Vosoughi, L. Wang, and S. Köse, "Bus-Invert Coding as a Low-Power Countermeasure Against Correlation Power Analysis Attack," Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), June 2019.
C38. M. A. Vosoughi and S. Köse, "Combined Distinguishers to Enhance the Accuracy and Success of Side Channel Analysis," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2019.
C37. M. A. Vosoughi and S. Köse, "Leveraging On-Chip Voltage Regulators Against Fault Injection Attacks," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), May 2019.
C36. L. Wang and S. Köse, "Reliability Enhanced On-Chip Digital LDO with Limit Cycle Oscillation Mitigation," Government Microcircuit Applications and Critical Technology Conference, March 2019.
C35. S. K. Khatamifard, L. Wang, S. Köse, and U. R. Karpuzcu, "POWERT Channels: A Novel Class of Covert Communication Exploiting Power Management Vulnerabilities," Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA), pp. 291 - 303, February 2019.
C34. L. Wang and S. Köse, "When Hardware Security Moves to the Edge and Fog," Proceedings of the IEEE International Conference on Digital Signal Processing (DSP'18), November 2018.
C33. M. Azhar and S. Köse, "Process, Voltage, and Temperature-stable Adaptive Duty Cycle based PUF," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1 - 5, May 2018.
C32. L. Wang and S. Köse, "Reliable On-Chip Voltage Regulation for Sustainable and Compact IoT and Heterogeneous Computing Systems," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. ?? - ??, May 2018.
C31. L. Wang, S. K. Khatamifard, U. R. Karpuzcu, and S. Köse, "Mitigation of NBTI Induced Performance Degradation in On-Chip Digital LDOs,"Proceedings of the IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 803 - 808, March 2018.
C30. A. W. Khan, T. Wanchoo, G. Mumcu, and S. Köse, "Implications of Distributed On-Chip Power Delivery on EM Side-Channel Attacks," IEEE International Conference on Computer Design (ICCD), pp. 329 - 336, November 2017.
C29. B. Pekoz, S. Köse, and H. Arslan, "Adaptive Windowing of Insufficient CP for Joint Minimization of ISI and ACI Beyond 5G," IEEE Annual International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC) , pp. 1 - 5, October 2017.
C28. A. Roohi, R. Demara, L. Wang, and S. Köse, "Secure Intermittent-Robust Computation for Energy Harvesting Device Security and Outage Resilience," IEEE Conference on Advanced and Trusted Computing, pp. 1 - 6, August 2017.
C27. S. K. Khatamifard, L. Wang, W. Yu, S. Köse, and U. R. Karpuzcu, "ThermoGater: Thermally-Aware On-Chip Voltage Regulation," Proceedings of the IEEE International Symposium on Computer Architecture (ISCA), pp. 120 - 132, June 2017.
C26. W. Yu and S. Köse, "A Lightweight AES Implementation Against Bivariate First-Order DPA Attacks," Proceedings of the ACM Workshop on Hardware and Architectural Support for Security and Privacy (HASP), pp. 1 - 7, June 2017.
C25. S. Köse, "Efficient and Secure On-Chip Reconfigurable Voltage Regulation for IoT Devices," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 369 - 374, May 2017.
C24. V. T. Alaparthy and S. Köse, "An Adaptive Senior Design Course with an Emphasis on Undergraduate Course Curriculum," Proceedings of the IEEE International Conference on Microelectronics System Education, pp. 59 - 62, May 2017.
C23. W. Yu and S. Köse, "Implications of Noise Insertion Mechanisms of Different Countermeasures Against Side-Channel Attacks," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. ?? - ??, May 2017.
C22. S. Köse, L. Wang, and R. Demara, "On-Chip Sensor Circle Distribution Technique for Real-Time Hardware Trojan Detection," Government Microcircuit Applications and Critical Technology Conference, March 2017.
C21. W. Yu, O. A. Uzun, and S. Köse, "Leveraging On-Chip Voltage Regulators as a Countermeasure Against Side-Channel Attacks," Proceedings of the IEEE/ACM Design Automation Conference (DAC), pp. 1 - 6, June 2015.
C20. M. E. Belviranli, W. Yu, and S. Köse, "Ultra-Fine Grain Power Management at Datapath-Level: Fact or Fiction," International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) WACI Session, March 2015.
C19. O. A. Uzun and S. Köse, "Regulator-Gating Methodology With Distributed Switched Capacitor Voltage Converters," Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pp. 13 - 18, July 2014.
C18. S. Köse, "Thermal Implications of On-Chip Voltage Regulation: Upcoming Challenges and Possible Solutions," Proceedings of the IEEE/ACM Design Automation Conference (DAC), pp. 1 - 6, June 2014.
C17. M. Azhar and S. Köse, "An Enhanced Pulse Width Modulator with Adaptive Duty Cycle and Frequency Control," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 958 - 961, June 2014.
C16. S. Köse, "Regulator-Gating: Adaptive Management of On-Chip Voltage Regulators," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 105 - 110, May 2014.
C15. S. Köse, I. Vaisband, and E. G. Friedman, "Digitally Controlled Wide Range Pulse Width Modulator for On-Chip Power Supplies," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2251 - 2254, May 2013.
C14. S. Köse, E. G. Friedman, R. M. Secareanu, and O. Hartin, "Current Profile of a Microcontroller to Determine Electromagnetic Emissions," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2650 - 2653, May 2013.
C13. S. Köse and E. G. Friedman, "Distributed Power Delivery for Energy Efficient and Low Power Systems," Asilomar Conference on Signals, Systems, and Computers, pp. 757 - 761, November 2012.
C12. S. Köse and E. G. Friedman, "Design Methodology to Distribute On-Chip Power in Next Generation Integrated Circuits," IEEE 27th Convention of Electrical and Electronics Engineers in Israel, pp. 1 - 4, November 2012.
C11. S. Köse and E. G. Friedman, "Power Delivery in Heterogeneous Integrated Circuits," IEEE CAS-FEST Workshop (in conjunction with ISCAS2012), May 2012.
C10. S. Köse, S. Tam, S. Pinzon, B. McDermott, and E. G. Friedman, "An Area Efficient On-Chip Hybrid Voltage Regulator," Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), pp. 398-403, March 2012.
C9. S. Köse and E. G. Friedman, "Fast Algorithms for IR Voltage Drop Analysis Exploiting Locality," Proceedings of the IEEE/ACM Design Automation Conference (DAC), pp. 996-1001, June 2011.
C8. S. Köse and E. G. Friedman, "Distributed Power Network Co-Design with On-Chip Power Supplies and Decoupling Capacitors," Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), June 2011.
C7. I. Savidis, S. Köse, and E. G. Friedman, "Power Grid Noise in TSV-Based 3-D Integrated Systems," Government Microcircuit Applications and Critical Technology Conference, March 2011.
C6. S. Köse and E. G. Friedman, "Simultaneous Co-Design of Distributed On-Chip Power Supplies and Decoupling Capacitors," Proceedings of the IEEE International SoC Conference, pp. 15 - 18, September 2010.
C5. S. Köse and E. G. Friedman, "An Area Efficient Fully Monolithic Hybrid Voltage Regulator," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2718 - 2721, May/June 2010.
C4. S. Köse and E. G. Friedman, "Fast Algorithms for Power Grid Analysis Based on Effective Resistance," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 3661 - 3664, May/June 2010.
C3. S. Köse and E. G. Friedman, "On-Chip Point-of-Load Voltage Regulator for Distributed Power Supplies," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 377 - 380, May 2010.
C2. S. Köse, E. Salman, and E. G. Friedman, "Shielding Methodologies in the Presence of Power/Ground Noise," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2277 - 2280, May 2009.
C1. S. Köse, E. Salman, Z. Ignjatovic, and E. G. Friedman, "Pseudo-Random Clocking to Enhance Signal Integrity," Proceedings of the IEEE International SoC Conference, pp. 47-50, September 2008.